Continuous‐time ΔΣ modulator having time‐interleaved switched‐capacitor brief‐return‐to‐zero DAC with first‐order jitter noise shaping

Abstract

A continuous-time delta-sigma modulator (CT DSM) having a time-interleaved switched-capacitor brief-return-to-zero DAC with first-order jitter noise shaping is proposed to reduce the sensitivity to clock jitter. The proposed CT DSM allows higher power efficiency and lower intersymbol interference by using a time-interleaved nearly full clock period integration with its current returning to zero briefly. Evaluation results indicate that the proposed third-order single-bit CT DSM operating at 168-MHz achieves 79.1 dB SNDR with 50% reduced DAC current for a 2-MHz signal bandwidth having 1% clock jitter as compared with conventional techniques.