Continuous runahead: Transparent hardware acceleration for memory intensive workloads

Hashemi, Milad; Mutlu, Onur; Yale, N Patt

doi:10.1109/micro.2016.7783764

Cited by 66 publications

(90 citation statements)

References 36 publications

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“…In a block group, the metadata block stores the sequence ID (SID), which is the unique number in the memory log area to represent a block group, and the metadata (BLK-1. Note that memory controllers are becoming increasingly more intelligent and complex to deal with various scheduling and performance management issues in multi-core and heterogeneous systems (e.g., [5], [6], [7], [8], [11], [12], [13], [14], [21], [25], [26], [27], [32], [33], [34], [35], [38], [39], [42], [45], [46], [49], [50], [51], [52], [53], [54], [61], [62], [64], [65], [66], [67], [68], [81], [84], [85], [86], [87], [88], [89], [97], [98], [108], [110], [112], [113],…”

Section: Eager Commitmentioning

confidence: 99%

Improving the Performance and Endurance of Persistent Memory with Loose-Ordering Consistency

Shu²,

Sun³

et al. 2024

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Persistent memory provides high-performance data persistence at main memory. Memory writes need to be performed in strict order to satisfy storage consistency requirements and enable correct recovery from system crashes. Unfortunately, adhering to such a strict order significantly degrades system performance and persistent memory endurance. This paper introduces a new mechanism, Loose-Ordering Consistency (LOC), that satisfies the ordering requirements at significantly lower performance and endurance loss. LOC consists of two key techniques. First, Eager Commit eliminates the need to perform a persistent commit record write within a transaction. We do so by ensuring that we can determine the status of all committed transactions during recovery by storing necessary metadata information statically with blocks of data written to memory. Second, Speculative Persistence relaxes the write ordering between transactions by allowing writes to be speculatively written to persistent memory. A speculative write is made visible to software only after its associated transaction commits. To enable this, our mechanism supports the tracking of committed transaction ID and multi-versioning in the CPU cache. Our evaluations show that LOC reduces the average performance overhead of memory persistence from 66.9% to 34.9% and the memory write traffic overhead from 17.1% to 3.4% on a variety of workloads.

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Section: Eager Commitmentioning

confidence: 99%

Improving the Performance and Endurance of Persistent Memory with Loose-Ordering Consistency

Shu²,

Sun³

et al. 2024

IEEE Trans. Parallel Distrib. Syst.

Self Cite

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show abstract

“…This type of code appears in benchmarks such as HashJoin ph2 (hj2). Most hardware prefetchers such as IMP cannot capture these memory accesses, because they require more than one arithmetic/logical operations; expensive hardware prefetchers, e.g., continuous runahead execution [2], can successfully prefetch this type of indirect memory access but only when runahead is sufficiently far and dependence chain can be successfully detected.…”

Section: A[b[i]] and A[b[c[i]]])mentioning

confidence: 99%

“…Each bucket in the hash table consists of a linked list. We used two different variations of this benchmark: (1) Hash Join 2EPB (HJ2) has only one node per bucket and (2). Hash Join 8EPB (HJ8) has three nodes per bucket; as such it performs memory accesses for the additional nodes.…”

Section: Benchmarksmentioning

confidence: 99%

“…But, to capture irregular access patterns, hardware prefetchers generally require very complex mechanisms. See, e.g., Hashemi et al [2] (describing continuous runahead execution). Yu et al [3] proposed a pure hardware mechanism called Indirect Memory Prefetcher (IMP), which was designed to capture a few different indirect memory access patterns (e.g.…”

Section: Introductionmentioning

confidence: 99%

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Informed Prefetching for Indirect Memory Accesses

Cavus

Sendag

2020

ACM Trans. Archit. Code Optim.

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Indirect memory accesses have irregular access patterns that limit the performance of conventional software and hardware-based prefetchers. To address this problem, we propose the Array Tracking Prefetcher (ATP), which tracks array-based indirect memory accesses using a novel combination of software and hardware. ATP is first configured by special metadata instructions, which are inserted by programmer or compiler to pass data structure traversal knowledge. It then calculates and issues prefetches based on this information. ATP also employs a novel mechanism for dynamically adjusting prefetching distance to reduce early or late prefetches. ATP yields average speedup of 2.17 as compared to a single-core without prefetching. By contrast, the speedup for conventional software and hardware-based prefetching is 1.84 and 1.32, respectively. For four cores, the average speedup for ATP is 1.85, while the corresponding speedups for software and hardwarebased prefetching are 1.60 and 1.25, respectively.

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“…Other than explicitly launching a helper thread, many proposals have dealt with reducing the chance a conventional microarchitecture is blocked [2], [13], [14], [19], [30], [38], [39], [41], [51], [55], [69], [73], [100]. Many designs share a theme of checkpointing important state, clean up some structures to allow further (speculative) execution.…”

Section: Background and Related Workmentioning

confidence: 99%

R3-DLA (Reduce, Reuse, Recycle): A More Efficient Approach to Decoupled Look-Ahead Architectures

Kondguli

Huang

2019

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Modern societies have developed insatiable demands for more computation capabilities. Exploiting implicit parallelism to provide automatic performance improvement remains a central goal in engineering future general-purpose computing systems. One approach is to use a separate thread context to perform continuous look-ahead to improve the data and instruction supply to the main pipeline. Such a decoupled look-ahead (DLA) architecture can be quite effective in accelerating a broad range of applications in a relatively straightforward implementation. It also has broad design flexibility as the look-ahead agent need not be concerned with correctness constraints. In this paper, we explore a number of optimizations that make the look-ahead agent more efficient and yet extract more utility from it. With these optimizations, a DLA architecture can achieve an average speedup of 1.4 over a state-of-the-art microarchitecture for a broad set of benchmark suites, making it a powerful tool to enhance single-thread performance.

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Continuous runahead: Transparent hardware acceleration for memory intensive workloads

Cited by 66 publications

References 36 publications

Improving the Performance and Endurance of Persistent Memory with Loose-Ordering Consistency

Improving the Performance and Endurance of Persistent Memory with Loose-Ordering Consistency

Informed Prefetching for Indirect Memory Accesses

R3-DLA (Reduce, Reuse, Recycle): A More Efficient Approach to Decoupled Look-Ahead Architectures

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