Contention-conscious transaction ordering in embedded multiprocessors

Khandelia, Mukul; Bhattacharyya, Shuvra S.

doi:10.1109/asap.2000.862398

Cited by 6 publications

(11 citation statements)

References 23 publications

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“…While the ordered transaction method is useful in its total elimination of run-time synchronization and arbitration overhead, the transaction partial order heuristic is able to improve the performance beyond what is achievable by a self-timed schedule even if synchronization and arbitration costs are negligible compared to actor execution times [6]. Such performance benefit is achieved by strategic positioning of the communication operations in ways that do not evolve from the natural evolution of self-timed schedules.…”

Section: Proc1mentioning

confidence: 95%

“…However, when IPC costs are not negligible, as is frequently and increasingly the case in practice, the problem of determining an optimal transaction order is NP-hard [6]. Thus, under nonzero IPC costs, we must resort to heuristics for efficient solutions.…”

Section: Proc1mentioning

confidence: 99%

“…The transaction order, which is enforced by special hardware, obviates the need for run-time synchronization and bus arbitration, and also enhances predictability. Also, if constructed carefully, it can in general lead to a more efficient pattern of actor/communication operations compared to an equivalent selftimed implementation [6].…”

Section: Introductionmentioning

confidence: 99%

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Mapping DSP Applications onto Self-timed Multiprocessors

Bhattacharyya¹,

Bambha²,

Khandelia³

et al. 2001

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BackgroundMultiprocessor implementation of DSP applications involves the interaction of several complex factors including scheduling, interprocessor communication, synchronization, iterative execution, and more recently, voltage scaling for low power implementation. Addressing any one of these factors in isolation is itself typically intractable in any optimal sense; at the same time, with the increasing trend toward multi-objective implementation criteria in the synthesis of embedded software, it is desirable to understand the joint impact of these factors. In this paper, we examine several high-level, intermediate representations that have been developed to analyze and optimize various multiprocessor DSP implementation factors and manage their interactions.The techniques discussed in this paper pertain to system specifications based on iterative synchronous dataflow (SDF) graphs [9]. Iterative SDF programming of DSP applications has been researched widely in the context of multiprocessor implementation, and numerous commercial DSP tools have been developed that incorporate SDF semantics. Examples of such tools include SPW by Cadence, COSSAP by Synopsys, and ADS by Hewlett-Packard.In SDF, an application is represented as a directed graph in which vertices (actors) represent computational tasks, edges specify data dependences, and the numbers of data values (tokens) produced and consumed by each actor is fixed. Delays on SDF edges represent initial tokens, and specify dependencies between iterations of the actors in iterative execution. For example, if tokens produced by the th invocation of actor are consumed by the th invocation of actor , then the edge contains two delays. Actors can be of arbitrary complexity. In DSP design environments, they typically range in complexity from basic operations such as addition or subtraction to signal processing subsystems such as FFT units and adaptive filters. We refer to an SDF representation of an applications an application graph.In this paper, we use a form of SDF called homogeneous SDF (HSDF) that is suitable for dataflow-based multiprocessor design tools. In HSDF, each actor transfers a single token to/from each incident edge. General techniques for converting SDF graphs into HSDF are developed in [9]. We refer to a homogeneous SDF graph as a dataflow graph (DFG). We represent a DFG by an ordered pair , where is the set of actors and is the set of edges. We refer to the source and sink actors of a DFG edge by and , we denote the delay on by , and we frequently represent by the ordered pair . We say that is an output edge of ; is an input edge of ; and is delayless if . The execution time or estimated execution time of an actor is denoted . Mapping an application graph onto a multiprocessor architecture includes three important steps -assigning actors to processors (processor assignment), ordering the actors assigned to each processor (actor ordering), and determining when each actor should commence execution. All of these tasks can either be performed at run...

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Section: Proc1mentioning

confidence: 95%

Section: Proc1mentioning

confidence: 99%

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Mapping DSP Applications onto Self-timed Multiprocessors

Bhattacharyya¹,

Bambha²,

Khandelia³

et al. 2001

Self Cite

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“…However,when IPC costs are not negligible, as is frequently and increasingly the case in practice, the problem of determining an optimal transaction order is NP-hard [6].This intractability has been shown to hold both under iterative and non-iterative execution of application graphs.Thus, under nonzero IPC costs, we must resort to heuristics for efficient solutions. Furthermore, the polynomial-time BFB algorithm is no longer optimal, and alternative techniques that account for IPC costs are preferable.…”

Section: Ordering Communicationmentioning

confidence: 99%

“…The transaction order, which is enforced by special hardware, obviates run-time synchronization and bus arbitration, and also enhances predictability. Also, if constructed carefully, it can in general lead to a more efficient pattern of actor/communication operations compared to an equivalent selftimed implementation [6].…”

Section: Introductionmentioning

confidence: 99%

Intermediate Representations for Design Automation of Multiprocessor DSP Systems

Bambha¹,

Kianzad²,

Khandelia³

et al. 2002

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Abstract. Self-timed scheduling is an attractive implementation style for multiprocessor DSP systems due to its ability to exploit predictability in application behavior, its avoidance of over-constrained synchronization, and its simplified clocking requirements. However, analysis and optimization of selftimed systems under real-time constraints is challenging due to the complex, irregular dynamics of selftimed operation. In this paper, we review a number of high-level intermediate representations for compiling dataflow programs onto self-timed DSP platforms, including representations for modeling the placement of interprocessor communication (IPC) operations; separating synchronization from data transfer during IPC; modeling and optimizing linear orderings of communication operations; performing accurate design space exploration under communication resource contention; and exploring alternative processor assignments during the synthesis process. We review the structure of these representations, and discuss efficient techniques that operate on them to streamline scheduling, communication synthesis, and power management of multiprocessor DSP implementations.

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