Contact vs bulk effects in N-semi-insulating-N and P-semi-insulating-P diodes

Manifacier, J.C.

doi:10.1016/j.sse.2012.10.003

Cited by 6 publications

(1 citation statement)

References 44 publications

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“…In a dual metal gate/HiK CMOS architecture, the high temperature activation of dopants can lead to a variation of the gate work function and an undesired increase of EOT due to residual oxygen diffusion to the HiK/channel interface. The Gate Last process (17,18,19) is the mandatory response to that issue as far as sub 1V supply voltage and near to band edges dual workfunctions are needed. At the sub 5 nm level, near zero variability processes will have to be introduced due to the near-to-molecular size of the devices.…”

Section: Nanoelectronics Scaling and The Use Of The 3rd Dimension To ...mentioning

confidence: 99%

(Plenary) The Future of Heterogeneous and Diversified ULSI Nanoelectronics

et al. 2013

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Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes level and face the challenge to approach zero variability. The main requirements will be to reduce leakage currents and reduce access resistances at the same time in order to fully exploit 3D integration at the device, elementary function, chip and system. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible

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Section: Nanoelectronics Scaling and The Use Of The 3rd Dimension To ...mentioning

confidence: 99%