Contact etch process optimization for RF process wafer edge yield improvement

Liu, Zhangli; He, Bingkui; Meng, Fanwen; Bao, Qiang; Sun, Yuhong; Sun, Shufeng; Zhou, Guangwei; Cao, Xiuliang; Xin, Haiwei

doi:10.1088/1674-4926/40/12/122402

Cited by 2 publications

(2 citation statements)

References 10 publications

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“…Figure S2 illustrates the bin-map distribution of the yield results for the device and shows that more than 35% of the total cells failed to reach the threshold, especially for the IGSS parameter. The majority of failed dies were distributed in the marginal region of the wafer, which may be related to the etching process [16]. IGSS and Vth tests could elucidate the gate oxide properties by further investigating the relationship between etching protocols and device electrical performances.…”

Section: Initial Etching Processmentioning

confidence: 99%

Sidewall Modification Process for Trench Silicon Power Devices

et al. 2023

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In this study, trench sidewall modification processes were designed to improve profile uniformity and thereby enhance the electrical performance of silicon power devices in large-scale production. The effects of trench sidewall modification on the morphology, structure and electrical properties were studied. Plasma-induced damage in etching processes was also observed and briefly explained. Straight and smooth sidewall profiles were achieved through adjusting the SF6/CHF3 proportion in a combined etchant gas flow in the main etching procedure. By comparing HRSEM images from different etching protocols, it was evident that an enhanced CHF3 flow formed a proper passivation of the sidewall, eliminating the ion damages that are common in current main etch steps. To address the impurities introduced from the etchant gas and improve the gate oxide uniformity, further steps of depolymerization were applied in a plasma asher chamber, followed by wet clean steps. In the meantime, the plasma-induced charge accumulation effect was reduced by UV curing. Improved trench sidewall profiles and the gate oxide uniformity contributed to a lower leakage current between the gate and source terminals, leading to an overall yield enhancement of device properties in large-scale silicon wafer fabrication.

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Section: Initial Etching Processmentioning

confidence: 99%

Sidewall Modification Process for Trench Silicon Power Devices

et al. 2023

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“…CMP is an ultra-precision mechanical technology that is widely used for polishing integrated circuit chips 1,2 and other materials. It can be used for nano-level polishing of many hard and brittle materials, including silicon, 1,2 glass, 3,4 ceramics, 5 sapphire.…”

mentioning

confidence: 99%

Thin Ferrite Wafer Uniformly Polished with Magnetic Attraction Method

Wang

Lin

et al. 2020

ECS J. Solid State Sci. Technol.

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When a ferrite substrate is used to prepare thin-film InSb Hall element chips, one surface of the ferrite wafer needs to be polished. The traditional chemical mechanical polishing (CMP) method, often used for polishing of ferrite wafers, has several problems: a long time to install and remove wafers, a little high debris rate, and high cost. Taking advantage of the fact that ferrite wafers can be magnetically attracted, a method using independent RuFeB magnets to attract and hold ferrite wafers is proposed. The polishing head holding the ferrite wafer can perform planetary rotary motion to achieve uniform polishing. The polishing head floats up and down freely on the polishing pad, without the requirements of matching and process accuracy in machining, mechanical linkage, and control. The roughness of the ferrite surface after polishing is about 0.18 μm, which meets the requirements for the substrate of InSb Hall element chips. With no debris, the efficiency of installing and removing wafers is 30 times higher than that of traditional methods. At the same time, compared with traditional CMP machine, the cost of CMP equipment made by this method is very low.

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Contact etch process optimization for RF process wafer edge yield improvement

Cited by 2 publications

References 10 publications

Sidewall Modification Process for Trench Silicon Power Devices

Sidewall Modification Process for Trench Silicon Power Devices

Thin Ferrite Wafer Uniformly Polished with Magnetic Attraction Method

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