Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes

Wong, Ming Ming; Wong, M. L. Dennis; Nandi, Asoke K.; Hijazin, Ismat

doi:10.1109/tvlsi.2011.2141693

Cited by 40 publications

(29 citation statements)

References 8 publications

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“…However, they report the bare minimal focus on the architectural design of the different symmetric lightweight security ciphers. All the lightweight ciphers defined so far have only look-up table-based S-boxes, which have their own limitations in hardware [18][19][20][21][22][23][24][25].…”

Section: Introductionmentioning

confidence: 99%

Lightweight S-Box Architecture for Secure Internet of Things

Prathiba

Bhaaskaran

2018

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Lightweight cryptographic solutions are required to guarantee the security of Internet of Things (IoT) pervasiveness. Cryptographic primitives mandate a non-linear operation. The design of a lightweight, secure, non-linear 4 × 4 substitution box (S-box) suited to Internet of Things (IoT) applications is proposed in this work. The structure of the 4 × 4 S-box is devised in the finite fields GF (2 4 ) and GF ( (2 2 ) 2 ). The finite field S-box is realized by multiplicative inversion followed by an affine transformation. The multiplicative inverse architecture employs Euclidean algorithm for inversion in the composite field GF ( (2 2 ) 2 ). The affine transformation is carried out in the field GF (2 4 ). The isomorphic mapping between the fields GF (2 4 ) and GF ( (2 2 ) 2 ) is based on the primitive element in the higher order field GF (2 4 ). The recommended finite field S-box architecture is combinational and enables sub-pipelining. The linear and differential cryptanalysis validates that the proposed S-box is within the maximal security bound. It is observed that there is 86.5% lesser gate count for the realization of sub field operations in the composite field GF ( (2 2 ) 2 ) compared to the GF (2 4 ) field. In the PRESENT lightweight cipher structure with the basic loop architecture, the proposed S-box demonstrates 5% reduction in the gate equivalent area over the look-up-table-based S-box with TSMC 180 nm technology.

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Section: Introductionmentioning

confidence: 99%

Lightweight S-Box Architecture for Secure Internet of Things

Prathiba

Bhaaskaran

2018

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“…Moreover, some structural optimization approaches have been widely employed to speed up the AES engines, such as parallel, pipelining, and subpipelining [117,41,30,159,163]. However, all the previous research focused on analyzing AES performance from the circuit perspective, based on the assumption that the 128-bit states can be input to AES engines immediately.…”

Section: High Security On-chip Bus Architecturementioning

confidence: 99%

“…Furthermore, since the composite field can be constructed by using different irreducible polynomials, [192] and [117] analyze and compare the complexity of the SB implementation with different constructions. In [192], how the coefficients of the field polynomials affect each block in the composite filed implementation of the SB transformation is illustrated, and then an optimum construction for the AES algorithm is presented.…”

Section: Aes Engine Optimizationmentioning

confidence: 99%

“…In [192], how the coefficients of the field polynomials affect each block in the composite filed implementation of the SB transformation is illustrated, and then an optimum construction for the AES algorithm is presented. The brief [117] In our survey, however, all the previous performance evaluations are based on the assumption that the AES states can be input to the encrypter/decrypter columnby-column immediately, without considering any on-chip bus overhead [81,68,67].…”

Section: Aes Engine Optimizationmentioning

confidence: 99%

“…Moreover, [192] and [117] analyze and compare the complexity of the SB implementation using different irreducible polynomials. The AES performance is also considered on the core structural level in [41], [146,30,159,77,163] [7], process data in the row-major order and are very low-efficiency to supply the rectangular array of bytes.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

Yang¹

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Area‐efficient and high‐speed hardware structure of hybrid cryptosystem (AES‐RC4) for maximizing key lifetime using parallel subpipeline architecture

Maniam

Sasilatha

2019

Concurrency and Computation

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Summary With the growth of wireless environments, confidential communication has become an important part of daily life. Generally, a wireless medium uses cryptography techniques when transmitting data to provide end‐to‐end protection. Most of the hardware‐efficient cryptosystems do not satisfy the security requirements. In this paper, we concentrate both on security issues and hardware efficiency and present an area‐efficient, high‐throughput hardware structure to implement a hybrid cryptosystem to avoid security problems. The security enhancements are done using a key enhancement process, and it is achieved by using a hybrid encryption cryptosystem. In this paper, we combine block and stream cipher encryption algorithms to frame the hybrid algorithm. We consider advanced encryption standard (AES) as the block cipher and Rivest cipher‐4 (RC4) as the stream cipher. Due to the hybrid systems, performance metrics, such as area, throughput, and power consumptions, are affected. Moreover, advanced arithmetic logic (ie, field arithmetic) combined with the on‐the‐fly key expansion technique is used to minimize area consumption, and parallel subpipeline technique is used to enhance the system throughput. The proposed hybrid architecture (AES‐RC4) is implemented in a field‐programmable gate array with a Xilinx tool.

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Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes

Cited by 40 publications

References 8 publications

Lightweight S-Box Architecture for Secure Internet of Things

Lightweight S-Box Architecture for Secure Internet of Things

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

Area‐efficient and high‐speed hardware structure of hybrid cryptosystem (AES‐RC4) for maximizing key lifetime using parallel subpipeline architecture

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