Construction of an Integrated Circuit Emission Model of a FPGA

Abstract

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A new methodology to extract the ICEM-CE internal activity block of a FPGA

“…ISE Xilinx tool performs a static timing analysis which gives a detailed report about the slack and the data path delays at the fast and slow PVT (Process/Voltage/Temperature) corners. For the construction of the IA, the pulse duration IJ is considered to be the median value of the interval whose boundaries are the maximum data path IJmax and the minimum data path IJmin given by the static timing report (4). The average dynamic current associated to a periodic pulsed waveform i(t) is calculated using (5).…”

“…A 1 probe, as defined by the IEC 61967-4 standard has been placed between the ground pins of the FPGA and the ground reference of the test board in order to measure the return current flowing outside the circuit. Models of the PDN of the FPGA and of the test board have been constructed from S parameter measurements and electromagnetic simulations and previously validated [4].…”

“…Several methods have been proposed for the construction of the IA block of the core. As proposed by the ICEM-CE model, the IA block could be extracted from IEC 61967-4 [3] measurements using an inverse method to recalculate internal currents sources [4] as described by Fig. 1.…”

A Parametric Conducted Emission Modeling Method of a Switching Model Power Supply (SMPS) Chip by a Developed Vector Fitting Algorithm

“…. (12) Using the full-wave analysis method, the Y-parameters were calculated. The results are shown in Figure 13.…”

“…As for these matters, various research has been reported in the past years [11][12][13]. Reference [14] gives an overview of the EMC research focusing on chip-level.…”