Constructing a Metrology Sampling Framework for In-line Inspection in Semiconductor Fabrication

Abstract

Due to the shrinking IC device geometries and increasing interconnect layers, process complexity has been rapidly increasing and leads to higher manufacturing costs and longer cycle time. Thus, in-line metrology is set at various steps to inspect the wafer in real time, which often causes lots of inspection costs and also increases cycle time. This study aims to develop a framework for in-line metrology sampling to determine the optimal sampling strategy in the light of different objectives to reduce extra cost and cycle time.