Constraint analysis for DSP code generation

Mesman, B.; Strik, M.T.J.; Timmer, A.H.; Meerbergen, J. van; Jess, J.A.G.

doi:10.1109/isss.1997.621673

Cited by 7 publications

(3 citation statements)

References 32 publications

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“…We will now explain how this transformation can be used to impose extra constraints on the DFG without excluding all feasible schedules. These constraints take the form of sequence edges between operations [8]. A sequence edge from an operation u to an operation v with integer weight w expresses the constraint that operation u should start at least w cycles before operation v. This means that any feasible schedule ö has to satisfy: ö(v) w ö(u) ) w. The techniques proposed in this paper break the symmetry in a DFG by introducing sequence edges with weight zero between symmetric operations.…”

Section: Breaking Symmetrymentioning

confidence: 99%

Identification and exploitation of symmetries in DSP algorithms

Eijk

Jacobs

Mesman

et al. 1999

Proceedings of the Conference on Design, Automation and Test in Europe

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In many algorithms, particularly those in the DSP domain, certain forms of symmetry can be observed. To efficiently implement such algorithms, it is often possible to exploit these symmetries. However, current hardware and software compilers show deficiencies, because they cannot identify them. In this paper we, we propose two techniques to automatically detect and utilize symmetry. Both techniques introduce sequence edges between operations such that the feasibility of the scheduling problem is preserved, while the symmetry is broken. In combination with existing techniques for constraint analysis, this enhances the quality of compilers considerably, as is shown by benchmark results.

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Section: Breaking Symmetrymentioning

confidence: 99%

Identification and exploitation of symmetries in DSP algorithms

Eijk

Jacobs

Mesman

et al. 1999

Proceedings of the Conference on Design, Automation and Test in Europe

Self Cite

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“…In this way, wrong decisions are prevented by checking whether they violate any constraints. In Mesman et al [1999], dataflows are expressed as precedence constraints. Latencies and initiation intervals are transferred to timing constraints.…”

Section: Solving the Phase Coupling Problem Staticallymentioning

confidence: 99%

Static resource models for code-size efficient embedded processors

Zhao

Mesman

Basten

2003

ACM Trans. Embed. Comput. Syst.

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Due to an increasing need for flexibility, embedded systems embody more and more programmable processors as their core components. Due to silicon area and power considerations, the corresponding instruction sets are often highly encoded to minimize code size for given performance requirements. This has hampered the development of robust optimizing compilers because the resulting irregular instruction set architectures are far from convenient compiler targets. Among other considerations, they introduce an interdependence between the tasks of instruction selection and scheduling. This so-called phase coupling is so strong that, in practice, instruction selection rather than scheduling is responsible for the quality of the schedule, which tends to disappoint. The lack of efficient compilation tools has also severely hampered the design space exploration of code-size efficient instruction sets, and correspondingly, their tuning to the application domain. In this article, we present an approach that reduces the need for explicit instruction selection by transferring constraints implied by the instruction set to static resource constraints. All resulting schedules are then guaranteed to correspond to a valid implementation with given instructions. We also demonstrate the suitability of this model to enable instruction set design (-space exploration) with a simple, well-understood and proven method long used in high-level synthesis (HLS) of ASICs. Experimental results show the efficacy of our approach.

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“…A network flow formulation in [6] was used to allocate address registers for DSP processors with significant savings in code size. Researchers in [10] perform register binding and instruction scheduling to minimize the number of registers and find tight schedules through the addition of sequencing relations. Memory bandwidth minimization for video and communications applications is studied in [11] in order to reduce the cost and complexity of memory architectures.…”

Section: Problem Description and Related Workmentioning

confidence: 99%

A network flow approach to memory bandwidth utilization in embedded DSP core processors

Gebotys

2002

IEEE Trans. VLSI Syst.

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This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors, 16-bit instructions which simultaneously access four words from memory are supported. A polynomial-time network flow methodology is used to allocate multiword accesses, including constant data-memory layout, while minimizing code size. Results show that improvements of up to 87% in terms of memory bandwidth are obtained compared to compiler-generated DSP code. This research is important for industry since this value-added technique can improve code size and utilize higher-memory bandwidths without increasing cost.

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Constraint analysis for DSP code generation

Cited by 7 publications

References 32 publications

Identification and exploitation of symmetries in DSP algorithms

Identification and exploitation of symmetries in DSP algorithms

Static resource models for code-size efficient embedded processors

A network flow approach to memory bandwidth utilization in embedded DSP core processors

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