Consistency of the Two Component Composite Modeling Framework for NBTI in Large and Small Area p-MOSFETs

Chaudhary, Ankush; Fernandez, Beryl; Parihar, Narendra; Mahapatra, S.

doi:10.1109/ted.2016.2630311

Cited by 25 publications

(6 citation statements)

References 23 publications

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“…9 versus the drain current for Core and I/O pMOS before and after stress. There is a good correlation between S Id /Id 2 and (g m /I d ) 2 characteristics, which indicates that the front gate noise can be modeled by the carrier number fluctuation ( N ) model [27], [28] based on trapping and de-trapping of charge in traps near the channel interface. Then S Id /Id 2 can be expressed as,…”

Section: B Degradation Of Low-frequency Characteristicmentioning

confidence: 94%

“…m is the transconductance, k is Boltzmann constant, T is temperature, λ is tunneling attenuation coefficient (∼0.1 nm for SiO 2 ), C ox is the gate capacitance per unit area, W and L are the gate width and length, respectively. By fitting (g m /I d )2 to S Id /Id 2 , S Vfb are extracted to be 4.75 × 10 −10 V 2 /Hz and 1.24 × 10 −9 V 2 /Hz for I/O pMOS before and after stress. According to (6), the trap densities N t for I/O pMOS before and after stress are calculated to be 5.20 × 10 17 eV −1 cm −3…”

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confidence: 99%

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Investigation of Negative Bias Temperature Instability Effect in Partially Depleted SOI pMOSFET

et al. 2020

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The negative bias temperature instability (NBTI) mechanisms for Core and input/output (I/O) devices from a 130 nm partially-depleted silicon on insulator (PDSOI) technology are investigated. The I/O device degrades more than the Core device under the same stress electric field due to the different gate oxide processes in these two types of devices. Both the oxide trap charge and interface trap lead to the transfer characteristics degradations of the device after NBTI. While the near interfacial traps result in the increase of low frequency noise (LFN). The trap densities near the silicon/gate oxide interface introduced by stress are extracted using the LFN method. NBTI-induced gate current increase is observed for Core device, but not for I/O device. It is result from the enhanced tunneling process, which is induced by the increase of electric field in the gate oxide after charge trapping at or near the channel interface. The gate width and length dependences of NBTI are observed. The enhanced NBTI degradation observed in short channel and narrow channel device is result from the enhanced NBTI effect at channel edge regions. The larger hole concentration is a main cause of the more serious NBTI degradation at the channel edge regions, including the nearby region of STI sidewall along the channel width direction and the gate edge region along the channel length direction. This conclusion is also verified by the TCAD simulations.INDEX TERMS Low frequency noise, negative bias temperature instability, silicon on insulator, TCAD simulation.

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Section: B Degradation Of Low-frequency Characteristicmentioning

confidence: 94%

mentioning

confidence: 99%

Investigation of Negative Bias Temperature Instability Effect in Partially Depleted SOI pMOSFET

et al. 2020

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“…The NBTI-induced traps have the same precursors as the TID-induced traps [22], [23]. There are neutron oxygen vacancies (i.e.…”

Section: A Nbti Effects Coupled By Tid Irradiation In Pdsoi Pmosfetmentioning

confidence: 99%

Research on Negative Bias Temperature Instability Effects Under the Coupling of Total Ionizing Dose Irradiation for PDSOI MOSFETs

et al. 2021

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The degradation mechanisms for pMOSFETs from a 130 nm partially-depleted silicon on insulator (PDSOI) technology under the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) are investigated. The TID and NBTI related degradations show an opposite trend as gate oxide scaling, which implies the different traps are activated during irradiation and NBTI stress. The radiation-induced traps can affect the NBTI effect of pMOSFET, especially for the ON bias irradiation. The irradiated I/O pMOSFET shows a smaller threshold voltage shift than the un-irradiated device under the same NBTI stress at the early stress stage. It may be contributed to the enhanced Fowler-Nordheim electron injection during NBTI stressing after ON bias irradiation. But the irradiation also increases the time exponent n from 0.11 to 0.13 for Core pMOSFETs and from 0.18 to 0.20 for I/O devices. It means that the NBTI degradations become worse after ON bias irradiation in a long time scale. This phenomenon is attributed to the change of trap characteristics caused by irradiation. As a result, the NBTI lifetime of Core device is reduced by nearly three orders of magnitude and the lifetime of I/O device is reduced by five times after ON bias irradiation at the rated operating voltage.INDEX TERMS MOSFET, negative bias temperature instability, silicon on insulator, total ionizing dose effect.

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“…A good overview of both models is presented in [9]. The RD model has also been extended to cope with stochastic effects in reduced geometries, leading to the introduction of the double-interface RD model [10], [11]. However, contrary to the original RD model, it also suffers from high computational cost when calculating ∆V th for AC stress, as it operates on a cycle-by-cycle basis [11].…”

Section: Bti Degradationmentioning

confidence: 99%

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors

Duch

Peón-Quirós

Weckx

et al. 2020

IEEE Trans. VLSI Syst.

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Aging effects in digital circuits change the switching characteristics of their transistors, resulting in timing violations that can lead to functional errors at the system level. In particular, bias temperature instability (BTI) is a degradation effect that changes the threshold voltage of transistors. Its effect is more prevalent as the scaling of transistor dimensions progresses. In this work, we present a method to enable defect-centric long-term modeling of BTI degradation that takes into account the effects of concrete workloads at the processor data path level. Based on this study, we propose a novel design flow to link the impact of BTI degradation at the transistor (∆V th), processor data path (e.g., maximum frequency) and application-functionality levels. This flow may be used to improve system correctness over the entire device lifetime, avoiding unsafe working points, or to achieve a graceful degradation of system characteristics. Our design flow is applicable to all types of digital circuits, including high-performance processors. However, in this specific work we focus on the domain of biosignal processing applications for wireless body sensor networks (WBSNs), whose pseudo-periodic nature interacts with the partially recoverable nature of BTI. Our results in this domain show, for a 32 nm implementation, a variation of up to 54.6 mV in the threshold voltage of the circuit transistors after one year of continuous operation, with an impact of 8.4 % in the maximum safe operating frequency. Such effects are expected to strongly worsen for longer lifetimes and more scaled technology nodes.

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Consistency of the Two Component Composite Modeling Framework for NBTI in Large and Small Area p-MOSFETs

Cited by 25 publications

References 23 publications

Investigation of Negative Bias Temperature Instability Effect in Partially Depleted SOI pMOSFET

Investigation of Negative Bias Temperature Instability Effect in Partially Depleted SOI pMOSFET

Research on Negative Bias Temperature Instability Effects Under the Coupling of Total Ionizing Dose Irradiation for PDSOI MOSFETs

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors

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