Consideration of age degradation in the RF performance of CMOS radio chips for high volume manufacturing

Ruberto, Mark N.; Maimon, Tzvi; Shemesh, Y.; Desormeaux, Andre Baguenier; Zhang, Weiquan; Yeh, Chih‐Jung

doi:10.1109/rfic.2005.1489872

Cited by 10 publications

(5 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Also the amount of degradation produced by changing VDD or PIN is similar. These observations denote similar relevance of the DC and RF components in the aging degradation, in agreement with some previous simulation [24] and experimental [13] works.…”

Section: A Nmos and Pmos Degradation With DC And Rf Stresssupporting

confidence: 92%

Aging in CMOS RF Linear Power Amplifiers: An Experimental Study

Aragones

Barajas

Crespo-Yepes

et al. 2021

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

An extensive experimental analysis of the HCI and BTI aging effects on RF linear power amplifiers (PA) is presented in this paper. Two different 2.45 GHz PA topologies have been implemented in a CMOS 65 nm technology, one based on a classical common-source (CS) and choke inductor, another one based on a complementary current-reuse (CR) circuit, both of them producing similar gain and output 1-dB compression point (P-1dB). These circuits have been stressed to produce accelerated aging degradation, by applying increasing supply (VDD) voltages, or increasing RF input powers (PIN). The degradation on the transistor parameters (threshold voltage and mobility), DC bias point (IDC current) and RF performance (gain, matching, compression point) have been simultaneously measured. This has allowed to observe how the reduced transistor degradation in CR PA results in a higher robustness in its RF parameters, compared to CS PA circuit. The equivalent RMS voltages have been proposed as an observable metric to assess the combined DC+RF stress in a PA circuit. This has been applied to a semi-analytical model, thus providing comprehension of the link between the conditions under which a circuit is operated, the degradation of the transistor parameters, and the effects on the DC current and RF performance.

show abstract

Section: A Nmos and Pmos Degradation With DC And Rf Stresssupporting

confidence: 92%

Aging in CMOS RF Linear Power Amplifiers: An Experimental Study

Aragones

Barajas

Crespo-Yepes

et al. 2021

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

show abstract

“…Degradation on simulation level is performed using the RelXpert aging simulator, which supports the simulation of BTI and HCD effects using a propriety AgeMOS model, as used in [18] [19] [20]. The goal is to capture the degradation influence on the operating point, hence the aging simulation has to be processed for every combination of the input parameter set.…”

Section: B Degradation and Operating Pointmentioning

confidence: 99%

An aging-aware transistor sizing tool regarding BTI and HCD degradation modes

Hellwege

Heidmann

Erstling

et al. 2015

2015 22nd International Conference Mixed Design of Integrated Circuits &Amp; Systems (MIXDES)

View full text Add to dashboard Cite

In this paper we present a tool based approach for an aging-aware design method. Extending the gm /I D sizing method by operating point-dependent degradation caused by BTI and HCD enables an innovative design flow. This design flow considers performance characteristics for a fresh circuit and also those of a degraded circuit at design time. Once the degradation from a single transistor is computed, the GMID-Tool does not need any further SPICE or aging simulation. The impact of the change in design methodology is shown for a typical differential amplifier structure.

show abstract

“…For aging, the dominant aging effects of hot carrier injection in NMOS and PMOS, as well as negative bias temperature instability in PMOS transistors, were considered. In the circuit simulations, the aged transistor models were then used to recompute the aged RF performance on the radio chip circuit blocks [1]. Electromigration effects were determined by parasitic extraction tools in looking at whether the inductor elements have enough metallization to carry the DC reliably.…”

Section: Figure 6: Rfic Design Flow For Performance Accuracy and Predmentioning

confidence: 99%

WLAN System, HW, and RFIC Architecture for the Intel PRO/Wireless 3945ABG Network Connection

Ruberto¹

2006

ITJ

View full text Add to dashboard Cite

The corporate challenge of being "one generation ahead" has prompted us to find new ways to improve our time to market, size, and cost of our WLAN products. By identifying the key issues which challenged us in our previous-generation products and by shifting our design effort to a platform-level optimization, we moved to a topdown approach in our Si and hardware architecture design flow. By taking the product-level requirements down to the last component on the board using this new methodology, we enabled smoother and cleaner platform integrations, as well as smaller and cheaper solutions. This paper summarizes the different architectural and functional changes in our products, from the system level down to the board/Si level. In addition, we discuss some of the design issues to ensure robust and reliable RF designs in our radio chips. The Intel ® PRO/Wireless 3945ABG Network Connection, which is a part of Intel ® Centrino ® Duo mobile technology, is the first Intel ® WLAN product to be conceived in this way.

show abstract

Consideration of age degradation in the RF performance of CMOS radio chips for high volume manufacturing

Cited by 10 publications

References 3 publications

Aging in CMOS RF Linear Power Amplifiers: An Experimental Study

Aging in CMOS RF Linear Power Amplifiers: An Experimental Study

An aging-aware transistor sizing tool regarding BTI and HCD degradation modes

WLAN System, HW, and RFIC Architecture for the Intel PRO/Wireless 3945ABG Network Connection

Contact Info

Product

Resources

About