Congestion Aware High Level Synthesis Combined with Floorplanning

Wu, Junhua; Ma, Chunmei; Huang, Baogui

doi:10.1109/paciia.2008.205

Cited by 8 publications

(7 citation statements)

References 5 publications

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“…Experimental results show that their method is more effective than the traditional method and CRSF (Congestion driven re-synthesis after floor planning) algorithm. [17] Another way of addressing the congestion problem in synthesis was also presented by Pandini D., Pileggi L., and Strojwas [15] in their paper. They focus on first addressing the problem of congestion minimization in logic synthesis during technology mapping.…”

Section: Introductionmentioning

confidence: 92%

Optimization of Physically-Aware Synthesis for Digital Implementation Flow

Geralla¹,

Guzman²,

Hora³

2018

IJET

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Synthesis is very important to have a high-quality implementation of every design. However, more accurate results could not be achieved if we will not consider the expected effects of routing delay introduced by placement and routing. This delay causes the poor timing correlation between the logical-only synthesis and Place and Route. . Now, tools with physical aware synthesis allow the user to integrate the physical information much early in the process. While such technique is readily available in the tools itself, there is no established flow to utilize the use of physical aware synthesis to the whole ASIC design process. Moreover, there’s lack of in-depth experimental analysis, specifically on commercially available designs, on the correlation of physically aware synthesis to the subsequent steps in the backend of the whole design process such as the place and route (PnR) and Timing Closure (STA). With this study, optimal flow for synthesis run is achieved through several experimental setups. Effects in place and route (PNR), and Static Timing Analysis (STA) is also observed and documented. Two different physically aware synthesis methodologies are proven to have improved timing correlation between the synthesis and PNR results. Power after signoff also improved significantly. Total runtime from synthesis to timing closure reduces because of much lesser violations in the first iteration alone.

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Section: Introductionmentioning

confidence: 92%

Optimization of Physically-Aware Synthesis for Digital Implementation Flow

Geralla¹,

Guzman²,

Hora³

2018

IJET

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“…As for congestion aware HLS, layout-friendly HLS approach [4] has been proposed to improve the congestion by changing the register/resource allocation of RTL architecture generated from HLS and by placement within slack time of interconnect delay and logic delay. The approach in [1] is based on Simulated Annealing with the cost function value which is obtained from a previous placement. J. Cong and et al [3] proposed a method of structural metrics called spreading score to handle the congestion problem at the HLS phase.…”

Section: Introductionmentioning

confidence: 99%

High Level Congestion Detection from C/C++ Source Code for High Level Synthesis

Tatsuoka

Kaneko

2020

IEICE Trans. Fundamentals

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High level synthesis (HLS) is a source-code-driven Register Transfer Level (RTL) design tool, and the performance, the power consumption, and the area of a generated RTL are limited partly by the description of a HLS input source code. In order to break through such kind of limitation and to get a further optimized RTL, the optimization of the input source code is indispensable. Routing congestion is one of such problems we need to consider the refinement of a HLS input source code. In this paper, we propose a novel HLS flow that performs code improvements by detecting congested parts directly from HLS input source code without using physical logic synthesis, and regenerating the input source code for HLS. In our approach, the origin of the wire congestion is detected from the HLS input source code by applying pattern matching on Program-Dependence Graph (PDG) constructed from the HLS input source code, the possibility of wire congestion is reported.

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“…However, as the abstraction level increases, the difficulty of congestion estimation is exacerbated due to the lack of physical information. Several HLS-based methods [8]- [11] are proposed to improve HLS scheduling or allocation algorithms to generate layout-friendly RTL models. [8]- [10] incorporate floorplanning to HLS and [11] summarizes multiple RTL metrics to evaluate the quality of HLS-generated models.…”

Section: Introductionmentioning

confidence: 99%

“…Several HLS-based methods [8]- [11] are proposed to improve HLS scheduling or allocation algorithms to generate layout-friendly RTL models. [8]- [10] incorporate floorplanning to HLS and [11] summarizes multiple RTL metrics to evaluate the quality of HLS-generated models. All of these methods aim at improving HLS algorithms, which is different from our problem that how to detect and eliminate congestion issues in the source code.…”

Section: Introductionmentioning

confidence: 99%

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

Zhao

Liang

Sinha

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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High-level synthesis (HLS) shortens the development time of hardware designs and enables faster design space exploration at a higher abstraction level. Optimization of complex applications in HLS is challenging due to the effects of implementation issues such as routing congestion. Routing congestion estimation is absent or inaccurate in existing HLS design methods and tools. Early and accurate congestion estimation is of great benefit to guide the optimization in HLS and improve the efficiency of implementation. However, routability, a serious concern in FPGA designs, has been difficult to evaluate in HLS without analyzing post-implementation details after Place and Route. To this end, we propose a novel method to predict routing congestion in HLS using machine learning and map the expected congested regions in the design to the relevant high-level source code. This is greatly beneficial in early identification of routability oriented bottlenecks in the high-level source code without running timeconsuming register-transfer level (RTL) implementation flow. Experiments demonstrate that our approach accurately estimates vertical and horizontal routing congestion with errors of 6.71% and 10.05% respectively. By presenting Face Detection application as a case study, we show that by discovering the bottlenecks in high-level source code, routing congestion can be easily and quickly resolved compared to the efforts involved in RTL level implementation and design feedback.

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Congestion Aware High Level Synthesis Combined with Floorplanning

Cited by 8 publications

References 5 publications

Optimization of Physically-Aware Synthesis for Digital Implementation Flow

Optimization of Physically-Aware Synthesis for Digital Implementation Flow

High Level Congestion Detection from C/C++ Source Code for High Level Synthesis

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

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