Optimization of Physically-Aware Synthesis for Digital Implementation Flow

Abstract

Synthesis is very important to have a high-quality implementation of every design. However, more accurate results could not be achieved if we will not consider the expected effects of routing delay introduced by placement and routing. This delay causes the poor timing correlation between the logical-only synthesis and Place and Route. . Now, tools with physical aware synthesis allow the user to integrate the physical information much early in the process. While such technique is readily available in the tools itself, there is no established flow to utilize the use of physical aware synthesis to the whole ASIC design process. Moreover, there’s lack of in-depth experimental analysis, specifically on commercially available designs, on the correlation of physically aware synthesis to the subsequent steps in the backend of the whole design process such as the place and route (PnR) and Timing Closure (STA). With this study, optimal flow for synthesis run is achieved through several experimental setups. Effects in place and route (PNR), and Static Timing Analysis (STA) is also observed and documented. Two different physically aware synthesis methodologies are proven to have improved timing correlation between the synthesis and PNR results. Power after signoff also improved significantly. Total runtime from synthesis to timing closure reduces because of much lesser violations in the first iteration alone.