Conflict Resolution by Matrix Reordering for DVB-T2 LDPC Decoders

Marchand, Cédric; Doré, Jean‐Baptiste; Conde-Canencia, Laura; Boutillon, Emmanuel

doi:10.1109/glocom.2009.5425755

Cited by 21 publications

(33 citation statements)

References 17 publications

(25 reference statements)

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“…Fig. 5 is an overview of the proposed layered decoder architecture (see [11] and [12] Table III. Synthesis Results for DVB-S2 LDPC decoder this figure, the NP block is made of 45 NP (Fig.…”

Section: Iv-c Resultsmentioning

confidence: 99%

Architecture and Finite Precision Optimization for Layered LDPC Decoders

Marchand

Conde-Canencia

Boutillon

2011

J Sign Process Syst

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Layered decoding is known to provide efficient and highthroughput implementation of LDPC decoders. In the practical hardware implementation of layered decoders, the performance is strongly affected by quantization. The finite precision model determines the area of the decoder, which is mainly composed of memory, especially for long frames. To be specific, in the DVB-S2,-T2 and -C2 standards, the memory can occupy up to 70% of the total area. In this paper, we focus our attention on the optimization of the number of quantization bits. Message saturation and memory size optimization are considered for the case of a DVB-S2 decoder. We show that the memory area can be reduced by 28% compared to the state-of-the-art, without performance loss.Index Terms-Low-density parity-check (LDPC) code, layered decoding, VLSI implementation, DVB-S2.

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“…Fig. 5 is an overview of the proposed layered decoder architecture (see [11] and [12] Table III. Synthesis Results for DVB-S2 LDPC decoder this figure, the NP block is made of 45 NP (Fig.…”

Section: Iv-c Resultsmentioning

confidence: 99%

Architecture and Finite Precision Optimization for Layered LDPC Decoders

Marchand

Conde-Canencia

Boutillon

2011

J Sign Process Syst

Self Cite

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“…Many papers in the literature consider this problem [6,5,7,8,9,10,11,12,13,14] and their solutions are briefly exposed in the following subsection.…”

Section: Memory Update Conflicts Problemmentioning

confidence: 99%

“…In [13,14] the parallelism is first reduced to eliminate most of the DDSM, then layers with DDSM are modified with specific scheduling. In [13] the presented design is efficient but limited to a parallelism of P = 40.…”

Section: Existing Workmentioning

confidence: 99%

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High-speed conflict-free layered LDPC decoder for the DVB-S2, -T2 AND -C2 standards

Marchand¹,

Conde-Canencia²,

Boutillon³

2013

SiPS 2013 Proceedings

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Layered decoding is known to provide efficient and highthroughput implementation of LDPC decoders. However, the implementation of layered architecture is not always straightforward because of memory update conflicts in the a posteriori information memory. In this paper, we focus our attention on a particular type of conflict that is due to multiple-diagonal sub-matrices in the DVB-S2, -T2 and -C2 parity-check matrices. We propose an original solution that combines repetition of the concerned layers and the write disable of the a posteriori information memory. The implementation of this solution on an FPGA-based LDPC decoder led to an average air throughput of 200 Mbit/s with a parallelism of 45 and a clock frequency of 300 MHz. Increasing the parallelism to 120 led to an average air throughput of 720 Mbit/s with a clock frequency of 400 MHz on CMOS technology.

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“…Thus, further efficient manipulation of the structure of the parity check matrix can make it suitable for layered decoding [27][28][29].…”

Section: Layered Decoding For Dvb-t2 Ldpc Codesmentioning

confidence: 99%

Improved synchronization, channel estimation, and simplified LDPC decoding for the physical layer of the DVB-T2 receiver

Sayed¹,

Elsabrouty

Shalash

2013

J Wireless Com Network

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The newly developed 2nd generation standard for digital video broadcasting (DVB-T2) emerges as a significant upgrade over its first generation predecessor DVB-T. The DVB-T2 standard targets an increased system throughput by at least 30% over the DVB-T. This article introduces algorithms in the signal processing chain to improve the mobile operation for DVB-T2. The proposed modified synchronization blocks, along with the improved channel estimation, show significant improvement compared to the results reported in the DVB-T2 implementation guide. In addition, state-of-the-art low-complexity algorithms in the bit processing chain, particularly in the LDPC decoder, are used to provide robustness and support throughput increase, while reducing the implementation complexity. The integrated system is simulated including implementation effects. The simulation results confirm the enhanced performance of the developed integrated model and provide better results compared to those reported in literature.

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Conflict Resolution by Matrix Reordering for DVB-T2 LDPC Decoders

Cited by 21 publications

References 17 publications

Architecture and Finite Precision Optimization for Layered LDPC Decoders

Architecture and Finite Precision Optimization for Layered LDPC Decoders

High-speed conflict-free layered LDPC decoder for the DVB-S2, -T2 AND -C2 standards

Improved synchronization, channel estimation, and simplified LDPC decoding for the physical layer of the DVB-T2 receiver

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