Conflict modelling and instruction scheduling in code generation for in-house DSP cores

Timmer, A.H.; Strik, M.; Meerbergen, J. van; Jess, J.A.G.

doi:10.1145/217474.217595

Cited by 40 publications

(24 citation statements)

References 12 publications

(2 reference statements)

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“…Many of the newly developed approaches to code generation for specialised DSP instructions [4], DSP specific code optimisation [12] and instruction scheduling [17] have transitioned out of the research labs and into product development and production.…”

Section: Introductionmentioning

confidence: 99%

Fast source-level data assignment to dual memory banks

Murray

Franke

2008

Proceedings of the 11th International Workshop on Software &Amp; Compilers for Embedded Systems

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Due to their streaming nature memory bandwidth is critical for most digital signal processing applications. To accommodate for these bandwidth requirements digital signal processors are typically equipped with dual memory banks that enable simultaneous access to two operands if the data is partitioned appropriately. Fully automated and compiler integrated approaches to data partitioning and memory bank assignment, however, have found little acceptance by DSP software developers. This is partly due to their inflexibility and inability to cope with certain manual data pre-assignments, e.g. due to I/O constraints. In this paper we present a different and more flexible approach, namely source-level dual memory assignment where code generation targets DSP-C, a standardised C language extension widely supported by industrial C compilers for DSPs. Additionally, we present a novel partitioning algorithm based on soft colouring that is more efficient and scalable than the currently known best integer linear programming algorithm, whilst achieving competitive code quality. We have evaluated our scheme on an Analog Devices TigerSHARC DSP and achieved speedups of up to 1.57 on 13 UTDSP benchmarks.

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Section: Introductionmentioning

confidence: 99%

Fast source-level data assignment to dual memory banks

Murray

Franke

2008

Proceedings of the 11th International Workshop on Software &Amp; Compilers for Embedded Systems

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“…The fifth column represents the number of iterations o ver the schedule analyzer (see Figure 2) before a feasible solution was found. The last 2 columns indicate the schedule freedom [4] Table 1 no camparison could be made to other approaches, because the re gister allocater and the schedulers available to us (several list schedulers) are unable to find any solution for the given constraints. The first experiment concerns an IIR filter of 23 operations, including fetching the coefficients and data from memory.…”

Section: Resultsmentioning

confidence: 99%

“…Therefore we will try a different approach based on the analysis of the constraints without exhaustively exploring the search space. T immer et al [4] successfully performed constraint analysis on a schedule problem using bipartite matching, but this w ork is dif ficult to extend to register constraints. Instead, this paper extends our previous work [15].…”

Section: Introductionmentioning

confidence: 99%

A constraint driven approach to loop pipelining and register binding

Mesman¹,

Strik²,

Timmer³

et al.

Proceedings Design, Automation and Test in Europe

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“…Researchers in [3] use graph based technique to perform code compaction, whereas in [4] a branch and bound scheduler and a heuristic search scheduler for the TMS320C2x processor are used to try to reduce the accumulator spilling and mode cost. A large integer linear programming (ILP) model was researched in [5] that performed simultaneous instruction selection, code compaction and register allocation.…”

Section: Problemmentioning

confidence: 99%

An efficient model for DSP code generation: performance, code size, estimated energy

Gebotys

Proceedings. Tenth International Symposium on System Synthesis (Cat. No.97TB100114)

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1.IntroductionHigh reliability, high performance and low cost are forcing higher levels of integration for VLSI embedded systems. As DSP applications are rapidly growing more complex, some designers are moving from full custom digital circuitry to programmable processors or in-house cores to obtain lower risk solutions. The DSP core is a DSP processor that can be reused and combined with program/data memory, dedicated logic, plus ASICs, and incorporated onto a large silicon chip, providing a cost efficient and flexible solution for many typical embedded applications requiring low power and high reliability. These systems demand small code size and high performance. Due to increasing complexities, high level compilation is a necessity. However the biggest drawback to both DSP processors or DSP core use is the code generation.The use of conventional code generation techniques and even compilers specifically designed for commercial DSP processors produce very inefficient code [8,4]. There are many more limitations placed upon code generation for the DSP processor than for the general purpose processor. The difficulty arises from non-homogeneous register sets, small number of very specialized registers, very specialized functional units, restricted connectivity, limited addressing, and highly irregular datapaths [8]. For example specialized functional units such as multiplier-accumulators and address calculation units are typically found in these architectures. Instructions take operands and store results of computations in well defined registers with limited connectivity. Instructions are highly interdependent and involve the use of modes, for example the mode classes typically involve product-shift and sign-extension. Some instructions will function differently depending upon the current mode setting and extra instructions to reset the mode are typically required. Limited addressing modes and the use of address registers are also typical. Code generation for DSP processors must meet tight timing constraints dictated typically by DSP throughput, and meet tight resource constraints. Given that these DSP processors must meet these requirements using very small code space (all on chip ROM), the code generation problem is a very difficult one [10]. Typically DSP processors are difficult to use and require long product development times even though the program being developed may be stored on chip in less than 1K program ROM. The need for decreasing time to market, development costs, and maintenance costs, demands the use of high level language compilation. All of these factors imply several challenges in writing efficient code generators for such DSP processors. This is even more difficult for the design of in-house DSP processor cores since retargetable compilation is also required. Problem Description and Related WorkThe following problem, problem 1 given below, is an important part of the code optimization problem that will be studied in this paper. For simplicity let us assume that an algorithm to implemen...

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Conflict modelling and instruction scheduling in code generation for in-house DSP cores

Abstract: Abstract

Cited by 40 publications

References 12 publications

Fast source-level data assignment to dual memory banks

Fast source-level data assignment to dual memory banks

A constraint driven approach to loop pipelining and register binding

An efficient model for DSP code generation: performance, code size, estimated energy

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