Fast source-level data assignment to dual memory banks

Abstract

Due to their streaming nature memory bandwidth is critical for most digital signal processing applications. To accommodate for these bandwidth requirements digital signal processors are typically equipped with dual memory banks that enable simultaneous access to two operands if the data is partitioned appropriately. Fully automated and compiler integrated approaches to data partitioning and memory bank assignment, however, have found little acceptance by DSP software developers. This is partly due to their inflexibility and inability to cope with certain manual data pre-assignments, e.g. due to I/O constraints. In this paper we present a different and more flexible approach, namely source-level dual memory assignment where code generation targets DSP-C, a standardised C language extension widely supported by industrial C compilers for DSPs. Additionally, we present a novel partitioning algorithm based on soft colouring that is more efficient and scalable than the currently known best integer linear programming algorithm, whilst achieving competitive code quality. We have evaluated our scheme on an Analog Devices TigerSHARC DSP and achieved speedups of up to 1.57 on 13 UTDSP benchmarks.

Exploiting architectural features of a computer vision platform towards reducing memory stalls

“…Platforms with multi-bank memory system mitigate the problem by mapping simultaneously requested data on different memory banks. Researchers have presented proposals to implement data mapping as a back-end compiler optimization [25,26] as well as by analyzing memory access pattern at higher levels [27][28][29] for single-processor systems. Other works, such as [30,31], propose approaches for mapping data of different applications to multiple memory banks in a multi-core environment.…”

Minimising Access Conflicts on Shared Multi-Bank Memory

“…In particular, there are many works on VLIW (in particular DSP) systems with dual-bank memories, e.g. by Saghir et al [29], Leupers and Kotte [18], Cho et al [6], Sipkova [31], Ko and Bhattacharyya [17] and Murray and Franke [21]. All of these works try to enable two simultaneous memory accesses by mapping the corresponding variables (or arrays) to different memory banks.…”

“…All of these works try to enable two simultaneous memory accesses by mapping the corresponding variables (or arrays) to different memory banks. While [29], [18] and [6] propose implementations as compiler backends, [31], [17] and [21] analyse the code on higher levels.…”

“…The typical solution approaches are greedy algorithms, other heuristics, or integer linear programming. [32] and [21] treat the assignment task as a graph colouring problem, like it is done in this work. However, all these works consider single processor systems and rely on conflict analysis techniques that are not applicable to multi-processor systems as discussed earlier.…”

Onboard Video Stabilization for Unmanned Air Vehicles

“…Memory location has been shown to influence algorithm run time by utilizing different sub banks [27] [16] [30]. Getz uses different memory banks to increase the speed of a dot product on a Blackfin [16].…”