Configurable Verification IP for UART

Harutyunyan, Stepan; Kaplanyan, Taron; Kirakosyan, Artak; Khachatryan, Haykaram

doi:10.1109/elnano50318.2020.9088878

Cited by 7 publications

(1 citation statement)

References 5 publications

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“…These are IP-Cores specifically designed to check the functionality of specific protocols, interfaces or functionalities both at a discrete level and in combination with other IPCores. An example of this type of VIP is presented in [17]. In some holistic verification methodologies, the input patterns and obtained results are reused in later design stages.…”

Section: Related Workmentioning

confidence: 99%

An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation

Cano-Quiveu

Ruiz-de-Clavijo-Vazquez

Bellido

et al. 2021

IEEE Access

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This paper introduces a design and on-chip verification framework for IPCores in FPGA platforms. The methodology of the proposed framework is based on the development of a high level software model, an HDL description of the IPCore and the verification of the system under test by the Autotest Core, an onchip verification core developed for this framework. The test pattern generation is done at the high level in software and used throughout the design and verification process. HDL simulation results can then be compared to on-chip results and get performance measurements from the Autotest Core. The Off-line testing is possible by using standard low-cost Flash storage (SD card). The proposed framework and methodology applied to PRESENT and SPONGENT cryptographic algorithms has shown over two orders of magnitude better performance than commercial tools like Xilinx's VIO and a hardware footprint of the verification cored below 3% of the available FPGA resources.

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Section: Related Workmentioning

confidence: 99%