Concurrent simulation of nearly identical digital networks

Ulrich, Ernst G.; Baker, Thomas

doi:10.1109/mc.1974.6323496

Cited by 171 publications

(12 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus, reconvergences of X values, where canceling of Xs may occur, are not evaluated correctly and the resulting signal values are not exact. In consequence, fault simulation based on n-valued logics like the parallel pattern single fault (PPSFP) and concurrent algorithm [1]- [4], are pessimistic and underestimate fault coverage 1 . If X values propagate into compaction logic as found in embedded deterministic test (EDT) or built-in self test (BIST) environments, the response signature may be corrupted.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Exact stuck-at fault classification in presence of unknowns

Hillebrecht

Kochte

Wunderlich

et al. 2012

2012 17th Ieee European Test Symposium (Ets)

View full text Add to dashboard Cite

Fault simulation is an essential tool in electronic design automation. The accuracy of the computation of fault coverage in classic n-valued simulation algorithms is compromised by unknown (X) values. This results in a pessimistic underestimation of the coverage, and overestimation of unknown (X) values at the primary and pseudo-primary outputs. This work proposes the first stuck-at fault simulation algorithm free of any simulation pessimism in presence of unknowns. The SAT-based algorithm exactly classifies any fault and distinguishes between definite and possible detects. The pessimism w. r. t. unknowns present in classic algorithms is discussed in the experimental results on ISCAS benchmark and industrial circuits. The applicability of our algorithm to large industrial circuits is demonstrated. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-Fault simulation is an essential tool in electronic design automation. The accuracy of the computation of fault coverage in classic n-valued simulation algorithms is compromised by unknown (X) values. This results in a pessimistic underestimation of the coverage, and overestimation of unknown (X) values at the primary and pseudo-primary outputs.This work proposes the first stuck-at fault simulation algorithm free of any simulation pessimism in presence of unknowns. The SAT-based algorithm exactly classifies any fault and distinguishes between definite and possible detects.The pessimism w. r. t. unknowns present in classic algorithms is discussed in the experimental results on ISCAS benchmark and industrial circuits. The applicability of our algorithm to large industrial circuits is demonstrated.

show abstract

Section: Introductionmentioning

confidence: 99%

“…This work presents the first fault simulation algorithm which computes the exact fault coverage of a test set in presence of X 1 In the following they are referred to as 3-valued fault simulators.…”

Section: Introductionmentioning

confidence: 99%

Exact stuck-at fault classification in presence of unknowns

Hillebrecht

Kochte

Wunderlich

et al. 2012

2012 17th Ieee European Test Symposium (Ets)

View full text Add to dashboard Cite

show abstract

“…Fault simulation algorithms such as the PPSFP (parallel pattern single fault propagation) and the concurrent algorithm [1][2][3][4] can be used to pessimistically estimate fault coverage for stuck-at and transition faults in presence of X values. Principally, these algorithms use an n-valued logic with limited number of symbols to compute the signal states in the faultfree and faulty circuit.…”

Section: Introductionmentioning

confidence: 99%

SAT-based fault coverage evaluation in the presence of unknown values

Kochte

Wunderlich

2011

2011 Design, Automation &Amp; Test in Europe

View full text Add to dashboard Cite

Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality. In case of unknown values (X-values), fault simulation is pessimistic and underestimates actual fault coverage, resulting in increased test time and data volume, as well as higher overhead for design-for-test. This work proposes a novel algorithm to determine fault coverage with significantly increased accuracy, offering increased fault coverage at no cost, or the reduction of test costs for the targeted coverage. The algorithm is compared to related work and evaluated on benchmark and industrial circuits. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-Fault simulation of digital circuits must correctly compute fault coverage to assess test and product quality. In case of unknown values (X-values), fault simulation is pessimistic and underestimates actual fault coverage, resulting in increased test time and data volume, as well as higher overhead for designfor-test. This work proposes a novel algorithm to determine fault coverage with significantly increased accuracy, offering increased fault coverage at no cost, or the reduction of test costs for the targeted coverage. The algorithm is compared to related work and evaluated on benchmark and industrial circuits.

show abstract

“…Simulation [5,15] of stuck faults is a resource intensive task and several acceleration techniques have been proposed [4,7,9,8,13]. Verification of industrial designs often involves simulation of large number of functional patterns that can be several million cycles long.…”

Section: Introductionmentioning

confidence: 99%

Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis

Bose

Agrawal

2007

2007 IEEE International Test Conference

View full text Add to dashboard Cite

Stuck fault coverage estimation for sequential circuits relies on a time expansion model, where combinational techniques are employed for each time-frame. Faults that are hard to detect and require a particular sequence of states are often incorrectly estimated to be detected. This problem is more evident for designs that exhibit low coverage either due to low testability or insufficient vectors that fail to exercise the required sequence of states. This paper illustrates how a simple state traversal analysis can mitigate this problem. For circuits with large number of sequential elements, we propose an entropy based technique that collapses the state graph to be analyzed. Experimental results for larger ISCAS benchmarks show that this technique reduces the coverage estimation error by as much as 50%.

show abstract

Concurrent simulation of nearly identical digital networks

Cited by 171 publications

References 0 publications

Exact stuck-at fault classification in presence of unknowns

Exact stuck-at fault classification in presence of unknowns

SAT-based fault coverage evaluation in the presence of unknown values

Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis

Contact Info

Product

Resources

About