Concurrent Separation Logic for Pipelined Parallelization

Bell, C.R.; Appel, Andrew W.; Walker, David

doi:10.1007/978-3-642-15769-1_10

Cited by 21 publications

(37 citation statements)

References 13 publications

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“…Indeed, Raza et al [2009] do not consider any program transformations, since the goal of that work is to identify memory separation of different commands, while Hurlin [2009] expresses optimizations as reordering rewrites on proof trees. Bell et al [2009] construct a proof of an already-transformed multithreaded program parallelized by the DSWP transformation [Ottoni et al 2005]. This approach assumes a specific pattern of (linear) dependencies in the while-loop consistent with DSWP, a specific pattern of sequential proof, and a fixed number of threads.…”

Section: Related Work In Detailmentioning

confidence: 99%

Proof-Directed Parallelization Synthesis by Separation Logic

Botinčan

Dodds

Jagannathan

2013

ACM Trans. Program. Lang. Syst.

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We present an analysis which takes as its input a sequential program, augmented with annotations indicating potential parallelization opportunities, and a sequential proof, written in separation logic, and produces a correctly synchronized parallelized program and proof of that program. Unlike previous work, ours is not a simple independence analysis that admits parallelization only when threads do not interfere; rather, we insert synchronization to preserve dependencies in the sequential program that might be violated by a naïve translation. Separation logic allows us to parallelize fine-grained patterns of resource usage, moving beyond straightforward points-to analysis. The sequential proof need only represent shape properties, meaning we can handle complex algorithms without verifying every aspect of their behavior.Our analysis works by using the sequential proof to discover dependencies between different parts of the program. It leverages these discovered dependencies to guide the insertion of synchronization primitives into the parallelized program, and to ensure that the resulting parallelized program satisfies the same specification as the original sequential program, and exhibits the same sequential behavior. Our analysis is built using frame inference and abduction, two techniques supported by an increasing number of separation logic tools. ACM Reference Format:Botinčan, M., Dodds, M., and Jagannathan, S. 2013. Proof-directed parallelization synthesis by separation logic.

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Section: Related Work In Detailmentioning

confidence: 99%

Proof-Directed Parallelization Synthesis by Separation Logic

Botinčan

Dodds

Jagannathan

2013

ACM Trans. Program. Lang. Syst.

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“…This specification is implicitly universally quantified for all assertions P , meaning that we can construct a predicate for any assertion. 1 New fut and req predicates can be constructed at run-time using newchan, meaning we can construct an arbitrarily large number of channels for use in the program.…”

Section: Verifying a Client Programmentioning

confidence: 99%

“…CSL has been extended to deal with dynamically-allocated locks [11,14,15] and re-entrant locks [12]. Others have extended separation logic or similar logics with primitive channels [13,1,24,18], and event driven programs [17].…”

Section: Related Work and Conclusionmentioning

confidence: 99%

Modular reasoning for deterministic parallelism

Dodds

Jagannathan

Parkinson

2011

Proceedings of the 38th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages

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NOTICE:We've been made aware that there's a bug in this paper that renders the reasoning unsound in certain corner-cases. We believe that the specifications can be fixed, and we're currently working on a solution. Please get in touch if you need more details. Thanks to Kasper Svendsen (kasv@itu.dk) for finding the bug.-Mike, Suresh and Matthew. Modular Reasoning for Deterministic Parallelism AbstractWeaving a concurrency control protocol into a program is difficult and error-prone. One way to alleviate this burden is deterministic parallelism. In this well-studied approach to parallelisation, a sequential program is annotated with sections that can execute concurrently, with automatically injected control constructs used to ensure observable behaviour consistent with the original program. This paper examines the formal specification and verification of these constructs. Our high-level specification defines the conditions necessary for correct execution; these conditions reflect program dependencies necessary to ensure deterministic behaviour. We connect the high-level specification used by clients of the library with the low-level library implementation, to prove that a client's requirements for determinism are enforced. Significantly, we can reason about program and library correctness without breaking abstraction boundaries.To achieve this, we use concurrent abstract predicates, based on separation logic, to encapsulate racy behaviour in the library's implementation. To allow generic specifications of libraries that can be instantiated by client programs, we extend the logic with higherorder parameters and quantification. We show that our high-level specification abstracts the details of deterministic parallelism by verifying two different low-level implementations of the library.

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“…To capture action repetition, the behavior of processes also can be described using a recursive definition, which must be paired with a contract. See for example the definition of process get_all in Listing 48 (lines [12][13][14][15].…”

Section: Reasoning With Historiesmentioning

confidence: 99%

“…Reasoning about several atomic synchronisers when they exchange their resources can lead to specify and verify Exchanger 1 from java.util.concurrent. To tackle this problem, techniques in which one can model interactions between atomic variables via message passing synchronisation [15] or channel based-based synchronisation [55] are helpful.…”

Section: Future Directionsmentioning

confidence: 99%

Specification and verification of synchronisation classes in Java : a practical approach

Amighi¹

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Concurrent Separation Logic for Pipelined Parallelization

Cited by 21 publications

References 13 publications

Proof-Directed Parallelization Synthesis by Separation Logic

Proof-Directed Parallelization Synthesis by Separation Logic

Modular reasoning for deterministic parallelism

Specification and verification of synchronisation classes in Java : a practical approach

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