Proof-Directed Parallelization Synthesis by Separation Logic

Botinčan, Matko; Dodds, Mike; Jagannathan, Suresh

doi:10.1145/2491522.2491525

Cited by 11 publications

(4 citation statements)

References 55 publications

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“…Program synthesis of parallel programs [8,48,52] often works by refining overly-coarse atomicity under programmer guidance, similar to the SOFRITAS approach. SOFRI-TAS's dynamic techniques scale to much larger programs, however, than synthesis currently supports.…”

Section: Optimizationsmentioning

confidence: 99%

Sofritas

et al. 2018

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Correctly synchronizing multithreaded programs is challenging and errors can lead to program failures such as atomicity violations. Existing strong memory consistency models rule out some possible failures, but are limited by depending on programmer-defined locking code. We present the new Ordering-Free Region (OFR) serializability consistency model that ensures atomicity for OFRs, which are spans of dynamic instructions between consecutive ordering constructs (e.g., barriers), without breaking atomicity at lock operations. Our platform, Serializable Ordering-Free Regions for Increasing Thread Atomicity Scalably (SOFRITAS), ensures a C/C++ program's execution is equivalent to a serialization of OFRs by default. We build two systems that realize the SOFRI-TAS idea: a concurrency bug finding tool for testing called SofriTest, and a production runtime system called SoPro. SofriTest uses OFRs to find concurrency bugs, including a multi-critical-section atomicity violation in memcached that weaker consistency models will miss. If OFRs are too coarse-grained, SofriTest suggests refinement annotations automatically. Our software-only SoPro implementation has high performance, scales well with increased parallelism, and prevents failures despite bugs in locking code. SoPro has an average overhead of just 1.59x on a single-threaded execution and 1.51x on sixteen threads, despite pthreads' much weaker memory model. CCS Concepts • Computer systems organization → Multicore architectures; • Software and its engineering → Runtime environments;

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Section: Optimizationsmentioning

confidence: 99%

Sofritas

et al. 2018

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“…Botincan et al propose a proof-directed parallelization synthesis which takes as input a sequential program with a proof in separation logic and outputs a parallelized counterpart by inserting barrier synchronizations [8,9]. Hurlin uses a proof-rewriting method to parallelize a sequential program's proof [15].…”

Section: Related Workmentioning

confidence: 99%

A Verification Technique for Deterministic Parallel Programs

Darabi

Blom

Huisman

2017

Lecture Notes in Computer Science

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A commonly used approach to develop parallel programs is to augment a sequential program with compiler directives that indicate which program blocks may potentially be executed in parallel. This paper develops a verification technique to prove correctness of compiler directives combined with functional correctness of the program. We propose syntax and semantics for a simple core language, capturing the main forms of deterministic parallel programs. This language distinguishes three kinds of basic blocks: parallel, vectorized and sequential blocks, which can be composed using three different composition operators: sequential, parallel and fusion composition. We show that it is sufficient to have contracts for the basic blocks to prove correctness of the compiler directives, and moreover that functional correctness of the sequential program implies correctness of the parallelized program. We formally prove correctness of our approach. In addition, we define a widely-used subset of OpenMP that can be encoded into our core language, thus effectively enabling the verification of OpenMP compiler directives, and we discuss automated tool support for this verification process.

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“…A successful fixpoint calculation tells us that it is possible to partition the heap given the assignment of cut-points, but it does not tell us how we would partition (6). This is because, for instance, we may lose track of the predicate c 2 → as it will be disposed (Listing 1, line 19) during the course of fix-point calculation before we even access c 1 → for the first time. We can solve this issue by recording each heaplet at the time it gets first assigned a label.…”

Section: B Proving Communication-free Parallelismmentioning

confidence: 99%

“…Furthermore, determining disjointness in our tree-based benchmarks requires successive unrollings of loop iterations before disjointness can be established, which is not implemented in their technique. Finally, recent work by Botinčan et al [19] describes a technique for separation logic-based parallelization of software threads. Their work is interesting in that they automatically insert synchronization to preserve dependencies in addition to a dependence analysis.…”

Section: Related Workmentioning

confidence: 99%

Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis

Winterstein

Bayliss

Constantinides

2014

2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines

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The capabilities of modern FPGAs permit the mapping of increasingly complex applications into reconfigurable hardware. High-level synthesis (HLS) promises a significant shortening of the FPGA design cycle by raising the abstraction level of the design entry to high-level languages such as C/C++. Applications using dynamic, pointer-based data structures and dynamic memory allocation, however, remain difficult to implement well, yet such constructs are widely used in software. Automated optimizations that aim to leverage the increased memory bandwidth of FPGAs by distributing the application data over separate banks of on-chip memory are often ineffective in the presence of dynamic data structures, due to the lack of an automated analysis of pointer-based memory accesses. In this work, we take a step towards closing this gap. We present a static analysis for pointer-manipulating programs which automatically splits heap-allocated data structures into disjoint, independent regions. The analysis leverages recent advances in separation logic, a theoretical framework for reasoning about heap-allocated data which has been successfully applied in recent software verification tools. Our algorithm focuses on dynamic data structures accessed in loops and is accompanied by automated source-to-source transformations which enable automatic loop parallelization and memory partitioning by off-the-shelf HLS tools. We demonstrate the successful loop parallelization and memory partitioning by our tool flow using three real-life applications which build, traverse, update and dispose dynamically allocated data structures. Our case studies, comparing the automatically parallelized to the non-parallelized HLS implementations, show an average latency reduction by a factor of 2.5 across our benchmarks.

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Proof-Directed Parallelization Synthesis by Separation Logic

Cited by 11 publications

References 55 publications

Sofritas

Sofritas

A Verification Technique for Deterministic Parallel Programs

Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis

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