Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs

Krasniewski, Andrzej

doi:10.1016/j.micpro.2008.03.008

Cited by 8 publications

(1 citation statement)

References 38 publications

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“…However, while the use of FPGAs for aerospace applications o®ers a number of important advantages, these devices are very sensitive to space harsh environment. [1][2][3] When a charged particle in the space environment strikes to active area of an integrated circuit, it generates a transient current pulse that can cause unwanted e®ects. 4 This phenomenon is able to produce an inversion in the stored value in memory cells and registers.…”

Section: Introductionmentioning

confidence: 99%

SEU-SECURE PARITY PREDICTION MULTIPLIER ON SRAM-BASED FPGAs

Gosheblagh

Mohammadi

2014

J CIRCUIT SYST COMP

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Modern SRAM-based¯eld programmable gate array (FPGA) devices o®er high capability in implementing satellites and space systems. Unfortunately, these devices are extremely sensitive to various kinds of unwanted e®ects induced by space radiations especially single-event upsets (SEUs) as soft errors in con¯guration memory. To face this challenge, a variety of soft error mitigation techniques have been adopted in literature. In this paper, we describe an area-e±cient multiplier architecture based on SRAM-FPGA that provides the self-checking capability against SEU faults. The proposed design approach, which is based on parity prediction, is able to concurrently detect the SEU faults. The implementation results of the proposed architecture reveal that the average area and delay overheads are respectively 25% and 34% in comparison with the plain version while the conventional duplication with comparison (DWC) architecture imposes 117% and 22% overheads. Moreover, the single and multi-upset fault injection experiments reveal that the proposed architecture averagely provides the failure coverage of 83% and 79% while the failure coverage of the duplicated structure is 85% and 84%, respectively for SEU and MEU faults.

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Section: Introductionmentioning

confidence: 99%