Concurrent Error Detectable Carry Select Adder with Easy Testability

Kito, Nobutaka; Takagi, Naofumi

doi:10.1109/tc.2019.2895074

Cited by 11 publications

(10 citation statements)

References 25 publications

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“…The proposed design with self-checking property is compared in terms of area overhead and fault coverage with the reported self-checking CSeA in [10] and [12]. Also, the proposed self-repairing HA is compared with self-repairing CoSA approach [19] and reduced precision TMR [17].…”

Section: Results and Benchmarkmentioning

confidence: 99%

“…It can be observed from Table . 4 that the proposed design requires on average 50% more transistor count as compared to the standard CSeA design without self-checking. Whereas, the required number of transistors are reduced by 76.76% and 115% as compared to [12] and [10], respectively. It should be noted that the proposed approach also requires 68.68% less transistor count as compared to our previous proposed self-checking CSeA [11].…”

Section: A Comparison With Self-checking Cseamentioning

confidence: 99%

“…In addition to the reduced area overhead, the proposed design possesses fault localization property and can detect multiple faults, with the condition that a single module should not have multiple faults, while [10] can only detect single fault at a time and [12] can only detect faults in odd number of bits without fault localization. In addition to the problem associated with odd number of erroneous bits, the approach in [12] is not totally self-checking because of the presence of logic sharing between the SUM and the propagated carry block. Any fault in the shared logic will easily get masked and cannot be detected with the parity prediction approach.…”

Section: A Comparison With Self-checking Cseamentioning

confidence: 99%

“…The design in [11] requires 12% less transistor count than the self-checking CSeA in [9]. In [12], a selfchecking CSeA is proposed using parity prediction approach in which the operands are provided to the adder along with their respective parities. It however cannot perform fault localization and has limited fault coverage, because it can only indicate fault if it occurs in odd number of bits.…”

Section: Introductionmentioning

confidence: 99%

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Self-Repairing Hybrid Adder With Hot-Standby Topology Using Fault-Localization

2020

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Effective self-repairing can be achieved if the fault along with its exact location can be determined. In this paper, a self-repairing hybrid adder is proposed with fault localization. It uses the advantages of ripple carry adder and carry-select adder to reduce the delay and area overhead. The proposed adder reduces the transistor count by 115% to 76.76% as compared to the existing self-checking carryselect adders. Moreover, the proposed design can detect and localize multiple faults. The fault-recovery is achieved by using the hot-standby approach in which the faulty module is replaced by a functioning module at run-time. In case of 3 consecutive faults, the probability of fault recovery has been found to be 96.1% for a 64-bit adder with 8 blocks, where each block has 9 full adders.

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Section: Results and Benchmarkmentioning

confidence: 99%

Section: A Comparison With Self-checking Cseamentioning

confidence: 99%

Section: A Comparison With Self-checking Cseamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Self-Repairing Hybrid Adder With Hot-Standby Topology Using Fault-Localization

2020

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“…Adders are primarily used as basic units in implementing digital signal processing (DSP) systems for applications like design of analog to digital converters (ADCs) and design of digital filters [8][9][10][11][12][13]. Different techniques are used in the design of a multi bit binary adder, for example ripple carry adder (RCA), carry increment adder (CIA), carry skip adder (CSkA), carry look ahead adder (CLA), carry select adder (CSlA), carry save adder (CSA), and carry bypass adder (CBA) [14][15][16][17][18].…”

Section: Introductionmentioning

confidence: 99%

High speed modified carry save adder using a structure of multiplexers

Hameed

Kathem

2021

IJECE

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Adders are the heart of data path circuits for any processor in digital computer and signal processing systems. Growth in technology keeps supporting efficient design of binary adders for high speed applications. In this paper, a fast and area-efficient modified carry save adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed in designing all stages of traditional CSA. By modifying the design of full adder in CSA, the complexity and area of the design can be reduced, resulting in reduced delay time. The VHDL implementations of CSA adders including (the proposed version, traditional CSA, and modified CSAs presented in literature) are simulated using Quartus II synthesis software tool with the altera FPGA EP2C5T144C6 device (Cyclone II). Simulation results of 64-bit adder designs demonstrate the average improvement of 17.75%, 1.60%, and 8.81% respectively for the worst case time, thermal power dissipation and number of FPGA logic elements.

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Design of an Improved Low-Power and High-Speed Booth Multiplier

Rafiq

Chaudhry

2021

Circuits Syst Signal Process

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Concurrent Error Detectable Carry Select Adder with Easy Testability

Cited by 11 publications

References 25 publications

Self-Repairing Hybrid Adder With Hot-Standby Topology Using Fault-Localization

Self-Repairing Hybrid Adder With Hot-Standby Topology Using Fault-Localization

High speed modified carry save adder using a structure of multiplexers

Design of an Improved Low-Power and High-Speed Booth Multiplier

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