Design of an Improved Low-Power and High-Speed Booth Multiplier

Rafiq, Ahsan; Chaudhry, Shabbir Majeed

doi:10.1007/s00034-021-01730-9

Cited by 5 publications

(1 citation statement)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The main drawback of a serial carry adder is the delay caused by waiting for the carry bit Ci to propagate one bit at a time when calculating each bit of S. To address this, we introduce the principle of a carry chain, a logic circuit that exists in an adder to propagate carry signals in parallel. Two signal bits, the carry generate bit (gi) and the carry propagate bit (pi), are introduced to make all bits' carry independent of lower bits' carry, allowing simultaneous generation of each bit's carry [6]. Thus, the delay in obtaining results is unrelated to the number of bits.…”

Section: Carry-lookahead Addermentioning

confidence: 99%

Enhancement Of A 32-By-32-Bit Signed Digital Multiplier: A Multi-Dimensional Optimization Approach

Cui,

Li,

Shang

2024

HSET

View full text Add to dashboard Cite

In the pursuit of enhanced performance in a 32-by-32-bit signed digital multiplier, optimizations were enacted on three critical fronts. Initial efforts focused on the integration of an advanced Booth encoding technique for the generation of three-bit control signals, meticulously crafted in the Verilog programming language. This approach, characterized by its restricted symbol expansion methodology, strategically curtails hardware resource expenditures, and diminishes power utilization during computational tasks. Subsequently, a sophisticated hybrid Wallace tree architecture was employed, offering a notable decrement in the delay of two XOR gates in contrast to the exclusive application of 3-2 and 4-2 compressors. This refinement not only augments the aggregation efficacy of partial products but also substantially accelerates operational velocity. Furthermore, the incorporation of a 64-bit carry-lookahead adder was instrumental in mitigating the latency induced by lower-order carry anticipation. To ascertain the multiplier's computational precision, a Verilog-constructed testbench file facilitated the assembly of 100,000 test vectors, with simulations executed in ModelSim yielding a verifiable accuracy rate of 100%.

show abstract

Section: Carry-lookahead Addermentioning

confidence: 99%