ConCISe: a compiler-driven CPLD-based instruction set accelerator

Kastrup, Bernardo; Bink, Arjan; Hoogerbrugge, Jan

doi:10.1109/fpga.1999.803671

Cited by 56 publications

(29 citation statements)

References 9 publications

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“…DPR offers important benefits for the designs implementation. Several architectures have been designed and have validated the DPR computing concept for the real time processing (Wirthlin and Hutchings, 1995;Vuillemin et al, 1996;Kastrup et al, 1999;Goldstein et al, 2000;Kessal et al, 2000;Donlin et al, 2005). However, optimal partitioning of an algorithm is not defined yet.…”

Section: Reconfigurability General Overviewmentioning

confidence: 99%

Dynamic Partial Reconfiguration Contribution on System on Programmable Chip Architecture for Motor Drive Implementation

N.¹

2012

American Journal of Engineering and Applied Sciences

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Problem statement: Nowadays, Reconfigurable System on Chip (RSoC) shows great potential in many high performance applications that benefit from Hardware customization. Approach: In this study, we present a design approach of FPGA based Controller for electromechanical system. In this way, we present solutions obtained by Hardware/Software Code sign methodology targeted for the implementation of a motor control drive system using Multiprocessor SoC (MPSoC) architecture. In order to enhance flexibility and performance of the considered system, we design different modules of HW current controller of electronic motor. A Dynamic Partial Reconfiguration (DPR) mechanism allowing switching on the fly between those modules is described. Results: Test and validation are done to validate the approach adopted. Experimental results confirmed the efficiency of the approach and allow us to determine more recommendations that should be considered while designing a RSoC control drive system. Conclusion/Recommendations: DPR enable flexible control system hardware design. This concept allows switching between different low order controls.

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Section: Reconfigurability General Overviewmentioning

confidence: 99%

Dynamic Partial Reconfiguration Contribution on System on Programmable Chip Architecture for Motor Drive Implementation

N.¹

2012

American Journal of Engineering and Applied Sciences

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“…Such prototypes include PRISC [5], Chimaera [6,7] and ConCISe [8]. The main limitation of these architectures is that the reconfigurable hardware supports only combinatorial circuits, in order to fit in the processor pipeline stages.…”

Section: Related Workmentioning

confidence: 99%

A pipelined configurable gate array for embedded processors

Lodi

Toma

Campi

2003

Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays - FPGA '03

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In recent years the challenge of high performance, low power retargettable embedded system has been faced with different technological and architectural solutions. In this paper we present a new configurable unit explicitly designed to implement additional reconfigurable pipelined datapaths, suitable for the design of reconfigurable processors. A VLIW reconfigurable processor has been implemented on silicon in a standard 0.18 µm CMOS technology to prove the effectiveness of the proposed unit. Testing on a signal processing algorithms benchmark showed speedups from 4.3x to 13.5x and energy consumption reduction up to 92%.

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“…The basic idea of such approach is to exploit both the general purpose processor capability to achieve medium performance for a large class of applications, and FPGA flexibility to implement application-specific computations. Thus far FPGA-augmented processors have predominantly assumed a simple general purpose core [1][2][3][4]. Considering the class of VLIW machines, two general research questions may be raised:…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study

Sima

Cotöfană

Vassiliadis

et al. 2002

Embedded Processor Design Challenges

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Abstract. The paper presents a case study on augmenting a TriMedia/CPU64 processor with a Reconfigurable (FPGA-based) Functional Unit (RFU). We first propose an extension of the TriMedia/CPU64 architecture, which consists of a RFU and its associated instructions. Then, we address the computation of the ¢ IDCT on such extended TriMedia, and propose a scheme to implement an 8-point IDCT operation on the RFU. Further, we address the decoding of Variable Length Codes and describe the FPGA implementation of a Variable Length Decoder (VLD) computing facility. When mapped on an ACEX EP1K100 FPGA from Altera, our 8-point IDCT exhibits a latency of 16 and a recovery of 2 TriMedia cycles, and occupies 42% of the FPGA's logic array blocks. The proposed VLD exhibits a latency of 7 TriMedia cycles when mapped on the same FPGA, and utilizes 6 of its embedded array blocks. By using the 8-point IDCT computing facility, an ¢ IDCT including all overheads can be computed with the throughput of 1/32 IDCT/cycle. Also, with the proposed VLD computing facility, a single DCT coefficient can be decoded in 11 cycles including all overheads. Simulation results indicate that by configuring each of the 8-point IDCT and VLD computing facilities on a different FPGA context, and by activating the contexts as needed, the augmented TriMedia can perform MPEG macroblock parsing followed up by a pel reconstruction with an improvement of 20-25% over the standard TriMedia.

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ConCISe: a compiler-driven CPLD-based instruction set accelerator

Cited by 56 publications

References 9 publications

Dynamic Partial Reconfiguration Contribution on System on Programmable Chip Architecture for Motor Drive Implementation

Dynamic Partial Reconfiguration Contribution on System on Programmable Chip Architecture for Motor Drive Implementation

A pipelined configurable gate array for embedded processors

A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study

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