Concepts of High-Level Language Computer Architecture

Chu, Yaohan

doi:10.1016/b978-0-12-174150-1.50007-0

Cited by 9 publications

(3 citation statements)

References 3 publications

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“…This would settle the interface crisis by integrated design approaches such as "top-down design" (]4) or "bottomup design", as practised in developing some high level language machines (survey: in ref. 5).…”

Section: Towards An Integration Of Design Methodsmentioning

confidence: 99%

Increasing hardware complexity---a challenge to computer architecture education

Hartenstein

1973

Proceedings of the 1st Annual Symposium on Computer Architecture - ISCA '73

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The paper starts with a survey over history and presentday situation of educational concepts and design methods in computer architecture. Complexity problems, bad design habits, cooperation problems between specialists, as well as their changing range of responsibility are covered, and the consequences of the developmental trends are discussed: now it is time for switching over to an integrated teaching of hardware/software design methods. The HIM scheme (hierarchy of interpretive modules) is suggested as a conceptual machine organization framework for modelling the implementation of language hierarchies. The application of the HIM scheme for better understanding of semantics, and for a derivation of designing guidelines is discussed.

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Section: Towards An Integration Of Design Methodsmentioning

confidence: 99%

Increasing hardware complexity---a challenge to computer architecture education

Hartenstein

1973

Proceedings of the 1st Annual Symposium on Computer Architecture - ISCA '73

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“…Significant amount of energy and time is invested in data transport between computation and memory units in the traditional von Neumann architecture [20]. To counter von Neumann issues, the neuromorphic architecture focuses on combining large number of computational nodes through an asynchronous clock.…”

Section: ) Neuromorphic Architecturesmentioning

confidence: 99%

On Memristors for Enabling Energy Efficient and Enhanced Cognitive Network Functions

Saleh

Koldehofe

2022

IEEE Access

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The high performance requirements of nowadays computer networks are limiting their ability to support important requirements of the future. Two important properties essential in assuring cost-efficient computer networks and supporting new challenging network scenarios are operating energy efficient and supporting cognitive computational models. These requirements are hard to fulfill without challenging the current architecture behind network packet processing elements such as routers and switches. Notably, these are currently dominated by the use of traditional transistor-based components. In this article, we contribute with an in-depth analysis of alternative architectural design decisions to improve the energy footprint and computational capabilities of future network packet processors by shifting from transistor-based components to a novel component named Memristor. A memristor is a computational component characterized by non-volatile operations on a physical state, mostly represented in form of (electrical) resistance. Its state can be read or altered by input signals, e.g. electrical pulses, where the future state always depends on the past state. Unlike in traditional von Neumann architectures, the principles behind memristors impose that memory operations and computations are inherently colocated. In combination with the non-volatility, this allows to build memristors at nanoscale size and significantly reduce the energy consumption. At the same time, memristors appear to be highly suitable to model cognitive functionality due to the state dependence transitions in the memristor. In cognitive architectures, our survey contributes to the study of memristorbased Ternary Content Addressable Memory (TCAM) used for storage of cognitive rules inside packet processors. Moreover, we analyze the memristor-based novel cognitive computational architectures built upon self-learning capabilities by harnessing from non-volatility and state-based response of memristors (including reconfigurable architectures, reservoir computation architectures, neural network architectures and neuromorphic computing architectures).

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“…In order to make Prolog a practical language, an attractive approach is to develop a high-level language machine [4] with both a high performance Prolog processor and a large real memory. Realizing a Prolog programming environment on the Prolog machine is also very important for developing practical application programs.…”

Section: Introductionmentioning

confidence: 99%

Design of a high-speed Prolog machine (HPM)

Nakazaki

Konagaya

Habata

et al. 1985

SIGARCH Comput. Archit. News

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Thispaper describes a High-speed Prolog Machine (HIM) architecture and its hardware structure, which are developed as a product of Fifth Generation Computer System (FGCS} project in Japan. HIM realizes high performance and provides a practical programming environment. A major HIM feature is a large memory capacity and specialized hardware for unification and stack operations.HIM has a compiler-oriented architecture with high-level stack-control instructions. Furthermore, the HIM architecture provides side-effect operations, nonlocal-exit control and multiprocess support primitives, which are effective to develop system programs. The performance is estimated at 280 KLIPS (Kilo Logical Inferences Per Second) in executing a deterministic "concatenate" Prolog program. The HIM processor is implemented with high-speed CCML {Current Mode Logic) chips and with I00 nanosecond machine cycle.

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Concepts of High-Level Language Computer Architecture

Cited by 9 publications

References 3 publications

Increasing hardware complexity---a challenge to computer architecture education

Increasing hardware complexity---a challenge to computer architecture education

On Memristors for Enabling Energy Efficient and Enhanced Cognitive Network Functions

Design of a high-speed Prolog machine (HPM)

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