Concatenating Packets in Variable-Length Input-Queued Packet Switches with Cell-Based and Packet-Based Scheduling

2012

IET Commun.

This paper presents a theoretical throughput analysis of two buffered-crossbar switches, called shared-memory crosspoint buffered (SMCB) switches, in which crosspoint buffers are shared by two or more inputs. In one of the switches, the sharedcrosspoint buffers are dynamically partitioned and assigned to the sharing inputs, and memory is sped up. In the other switch, inputs are arbitrated to determine which of them accesses the shared-crosspoint buffers, and memory speedup is avoided. SMCB switches have been shown to achieve a throughput comparable to that of a combined input-crosspoint buffered (CICB) switch with dedicated crosspoint buffers to each input but, with less memory than a CICB switch. The two analyzed SMCB switches use random selection as the arbitration scheme. We model the states of the shared crosspoint buffers of the two switches using a Markov-modulated process and prove that the throughput of the proposed switches approaches 100% under independent and identically distributed uniform traffic. In addition, we provide numerical evaluations of the derived formulas to show how the throughput approaches asymptotically to 100%.

Section: F Discussion Of Nonblocking Probability Under Hot Spot and mentioning

confidence: 99%

Throughput analysis of shared-memory crosspoint buffered packet switches

Dong

2012

IET Commun.

“…Here, the "X" mark indicates that the buffer at VOMQ(k) is occupied by cells from other flows. Assuming k = 3 and no other cell arrival or departure during this time (1) OM (2) OP (2,2) . .…”

Section: In-sequence Cell Forwarding Mechanismmentioning

confidence: 99%

“…For example, switches that require long configuration time may need to use a long internal segment and time to transmit data while switches with fast configuration times may use a smaller segment size. Therefore, the configuration time of a switch must be kept to the shortest possible for a fast and efficient reconfiguration [2].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Split-Central-Buffered Load-Balancing Clos-Network Switch With In-Order Forwarding

Sule

IEEE/ACM Trans. Networking

Dong

et al. 2019

Self Cite

We propose a configuration scheme for a loadbalancing Clos-network packet switch that has split central modules and buffers in between the split modules. Our splitcentral-buffered Load-Balancing Clos-network (LBC) switch is cell based. The switch has four stages, namely input, centralinput, central-output, and output stages. The proposed configuration scheme uses a pre-determined and periodic interconnection pattern in the input and split central modules to load-balance and route traffic. The LBC switch has low configuration complexity. The operation of the switch includes a mechanism applied at input and split-central modules to forward cells in sequence. The switch achieves 100% throughput under uniform and nonuniform admissible traffic with independent and identical distributions (i.i.d.). These high switching performance and low complexity are achieved while performing in-sequence forwarding and without resorting to memory speedup or central-stage expansion. Our discussion includes throughput analysis, where we describe the operations that the configuration mechanism performs on the traffic traversing the switch, and proof of in-sequence forwarding. A simulation study is presented as a practical demonstration of the switch performance on uniform and nonuniform i.i.d. traffic.Index Terms-Clos-network switch, load-balancing switch, inorder forwarding, high performance switching, packet scheduling, packet switching.

“…Packet concatenation has been considered for IQ [21] and Combined Input-Crosspoint Queued (CICQ) switches [17]. However, the results may include the architecture-dependent effects.…”

Section: Introductionmentioning

confidence: 99%

Avoiding Speedup from Bandwidth Overhead in a Practical Output-Queued Packet Switch

Cai

2011 IEEE International Conference on Communications (ICC)

Kijkanjanarat

2011

Self Cite

We study a time-slotted and synchronous outputqueued switch that uses packet concatenation to reduce bandwidth overhead, or CS-OQ switch. The CS-OQ switch avoids memory speedup through the use of dedicated optical lines connecting inputs to outputs. The dedicated lines are combined with virtual input queues (VIQs) at the outputs and segmentation queues at the inputs. The segmentation queues are used for packet concatenation. We show that the performance of the CS-OQ switch approaches that of an ideal output queued switch, or asynchronous OQ (A-OQ) switch by selecting a suitable segmentation length in combination with packet concatenation.Index Terms-Output queued switch, synchronous switch, asynchronous switch, packet segmentation, concatenation, bandwidth utilization, packet delay. I. INTRODUCTIONAn Output-Queued (OQ) switch provides optimum switching performance as compared to switches with other queuing strategies. In an OQ switch, a packet is placed to the destined output queue right after it arrives in the input. The forwarding of a packet takes P L i /R i units of time, where P L i is the packet length at input i (for 1 ≤ i ≤ N ), and R i is the link data rate. If a queue at the output is shared by all inputs, each output queue is accessed at a rate R = N R i . To support such a rate, the required access time t mem of the output memory