Computing Models for FPGA-Based Accelerators

Herbordt, Martin C.; Gu, Yongfeng; VanCourt, T.; Model, J.; Sukhwani, Bharat; Chiu, Matt

doi:10.1109/mcse.2008.143

Cited by 28 publications

(16 citation statements)

References 28 publications

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“…In other words it is up to the designer what the architecture of the system will be. In [11] a good survey on the computing models for FPGA-based accelerators is presented. The authors of this survey claim that FPGAs are good tools for designing high-performance computers (HPC) because of their flexible micro-architecture.…”

Section: Fpgas For Hardware Acceleration Of Image and Video Processingmentioning

confidence: 99%

Embedded platform for local image descriptor based object detection

Kapela

Gugała

Śniatała

et al. 2015

Applied Mathematics and Computation

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Section: Fpgas For Hardware Acceleration Of Image and Video Processingmentioning

confidence: 99%

Embedded platform for local image descriptor based object detection

Kapela

Gugała

Śniatała

et al. 2015

Applied Mathematics and Computation

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“…A number of general purpose and specialized hardware systems are being investigated [10,12,17,19,[22][23][24][25][26][34][35][36]. Each step involves billions of arithmetic operations that model the interactions between thousands of particles that additionally must be repeated millions or more times.…”

Section: Background and Motivationmentioning

confidence: 99%

“…Alternate computer hardware technologies have attracted considerable interest for improving the time-to-solution of MD simulations. A number of general purpose and specialized hardware systems are being investigated [10,12,17,19,[22][23][24][25][26][34][35][36].…”

Section: Background and Motivationmentioning

confidence: 99%

Performance modeling of microsecond scale biological molecular dynamics simulations on heterogeneous architectures

Agarwal

Hampton²,

Poznanovic

et al. 2012

Concurrency and Computation

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Performance improvements in biomolecular simulations based on molecular dynamics (MD) codes are widely desired. Unfortunately, the factors, which allowed past performance improvements, particularly the microprocessor clock frequencies, are no longer increasing. Hence, novel software and hardware solutions are being explored for accelerating performance of widely used MD codes. In this paper, we describe our efforts on porting, optimizing and tuning of Large-scale Atomic/Molecular Massively Parallel Simulator, a popular MD framework, on heterogeneous architectures: multi-core processors with graphical processing unit (GPU) accelerators. Our implementation is based on accelerating the most computationally expensive non-bonded interaction terms on the GPUs and overlapping the computation on the CPU and GPUs. This functionality is built on top of message passing interface that allows multi-level parallelism to be extracted even at the workstation level with the multi-core CPUs and allows extension of the implementation on GPU-enabled clusters. We hypothesize that the optimal benefit of heterogeneous architectures for applications will come by utilizing all possible resources (for example, CPU-cores and GPU devices on GPU-enabled clusters). Benchmarks for a range of biomolecular system sizes are provided, and an analysis is performed on four generations of NVIDIA's GPU devices. On GPU-enabled Linux clusters, by overlapping and pipelining computation and communication, we observe up to 10-folds application acceleration in multi-core and multi-GPU environments illustrating significant performance improvements. Detailed analysis of the implementation is presented that allows identification of bottlenecks in algorithm, indicating that code optimization and improvements on GPUs could allow microsecond scale simulation throughput on workstations and inexpensive GPU clusters, putting widely desired biologically relevant simulation time-scales within reach of a large user community. In order to systematically optimize simulation throughput and to enable performance prediction, we have developed a parameterized performance model that will allow developers and users to explore the performance potential of future heterogeneous systems for biological simulations.workload, off-loading the non-bonded calculations onto the GPUs provides the best utilization of the resources. On the other hand, the case of the PME method requires the use of FFTs, which results in significant communication between the concurrent elements as well as a slightly smaller requirement of the FP arithmetic. Overall, the results show that a single workstation with a total of eight Figure 2. Improvement in time-to-solution with GPU-enabled LAMMPS for the cut-off based MD simulations. Tests were performed with Tesla C1060 GPUs and hardware configuration B (Table II); all tests were performed for 1000 steps with 2 fs time-step (time-to-solution for CPU-only version in the inset). 1364 P. K. AGARWAL ET AL.CPU-cores (two quad-core processors) and one, two and four...

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“…Production chips with hundreds of CPU cores are projected to be delivered in the next several years. 1 Replicating cores, however, is only one of several viable strategies for developing next-generation highperformance computing (HPC) architectures.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Middle Product Algorithm on Linear Processor Arrays

Milovanovic

Stojcev

2014

J CIRCUIT SYST COMP

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This paper presents the design, implementation and performance evaluation of the linear processor array accelerator for matrix multiplication. We call it matrix multiplication processor (MMP). The MMP is composed of n processing elements (PEs) connected in a chain, distributed memory, and dedicated address generator unit (AGU) to generate memory addresses. By using this approach, address generation does not increase the processing time. The AGU is one major di®erence in the proposed architecture compared to graphics processing units (GPUs) that use ALUs to create addresses. MMP is based on FPGA technology since this circuits possess extreme degree of parallelism and ability to customize the RAM and data path architecture to the computation. We have considered performance metrics of the proposed architecture in the sense of number of PEs, execution time, speedup, e±ciency and gain factor. We have implemented AGU and PE in Xilinx Spartan 2E FPGAs using ISE 9.01 as a software tool. We compare our design with respect to the execution time, number of PEs, AT measure, speedup and e±ciency with other solutions proposed in the literature.

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Computing Models for FPGA-Based Accelerators

Cited by 28 publications

References 28 publications

Embedded platform for local image descriptor based object detection

Embedded platform for local image descriptor based object detection

Performance modeling of microsecond scale biological molecular dynamics simulations on heterogeneous architectures

Implementation of Middle Product Algorithm on Linear Processor Arrays

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