Computer Systems Based on Silicon Photonic Interconnects

Krishnamoorthy, Ashok V.; Ho, Ron; Zheng, Xuezhe; Schwetman, Herb; Lexau, Jon; Koka, Pranay; Li, Guoliang; Shubin, Ivan; Cunningham, J. E.

doi:10.1109/jproc.2009.2020712

Cited by 389 publications

(146 citation statements)

References 53 publications

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“…This has fueled significant research and development work in this area in the past few years. [1][2][3][4][5][6][7][8][9][10][11] Many silicon-based active photonics components, such as high-speed modulators and Ge photodetectors [4][5][6][7][8][9][10] have been demonstrated on submicron waveguides. However, submicron SOI waveguides still suffer from high fiber coupling loss, high polarization dependent loss, and large waveguide birefringence and phase noise.…”

mentioning

confidence: 99%

High-speed Ge photodetector monolithically integrated with large cross-section silicon-on-insulator waveguide

Feng¹,

Liao²,

Dong³

et al. 2009

Applied Physics Letters

185

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We demonstrate a compact, high speed Ge photodetector efficiently butt-coupled with a large cross-section silicon-on-insulate (SOI) waveguide in which the Ge p-i-n junction is placed in the horizontal direction to enable very high speed operation. The demonstrated photodetector has an active area of only 0.8×10 μm2, greater than 32 GHz optical bandwidth, and a responsivity of 1.1 A/W at a wavelength of 1550 nm. Very importantly the device can readily be integrated with high performance wavelength-division-multiplexing filters based on large cross-section SOI waveguide to form monolithic integrated silicon photonics receivers for multichannel terabit data transmission applications.

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mentioning

confidence: 99%

High-speed Ge photodetector monolithically integrated with large cross-section silicon-on-insulator waveguide

Feng¹,

Liao²,

Dong³

et al. 2009

Applied Physics Letters

185

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“…This is far from the 2015 energy target for tunable WDM filters of 30 fJ/bit [2] or reported values of 15 fJ/bit [11] using under-etched waveguides and flexible wavelength registration. Another way to improve the power consumption could come from (1) fabrication, where a better control over the silicon waveguide thickness could lower the maximum tuning range required [12], (2) from design, by using designs with larger FSR and thus increasing the wavelength shift for given power consumption or (3) by an increased bitrate.…”

Section: B Thermal Tuningmentioning

confidence: 83%

“…Independent of the actual operation temperature, one can expect (in a worst case scenario) the need to tune the receiver filter grid up to a full FSR to lock it to an incoming laser grid. If each channel of our receiver will handle a bitrate of 20 Gb/s (following the reasoning of [2]), this would mean a worst-case power consumption of 3.7 pJ/bit for design 1 and a 5.07 pJ/bit for design 2. Note that this is a worst-case scenario, on average one device will consume half of this power (corresponding to only half a Fig.…”

Section: B Thermal Tuningmentioning

confidence: 99%

Fabrication-Tolerant Four-Channel Wavelength-Division-Multiplexing Filter Based on Collectively Tuned Si Microrings

Heyn

Coster

Verheyen

et al. 2013

J. Lightwave Technol.

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Abstract-We demonstrate a robust, compact and low-loss four-channel wavelength-division multiplexing (WDM) filter based on cascaded double-ring resonators (2RR) in silicon. The flat-top channel response obtained by the second-order filter design is exploited to compensate for the detrimental effects of local fabrication variations and their associated phase errors on the ring-based filter response. Full wafer-scale characterization of a cascaded, four-channel 2RR filter with channel spacing of 300 GHz shows an average worst-case insertion loss below 1.5 dB and an average worst-case crosstalk below 18 dB across the wafer, representing a substantial improvement over a first-order based ring (1RR) design. The robust 2RR filter design enables the use of a simple collective thermal tuning mechanism to compensate for global fabrication variations as well as for global temperature fluctuations of the WDM filter, the WDM laser source, or both. Highly uniform collective heating is demonstrated using integrated doped silicon heaters. The compact filter footprint of less than per channel enables straightforward scaling of the WDM channel count to 8 channels and beyond. Such low-loss collectively tuned ring-based WDM filters can prove beneficial in scaling the bandwidth density of chip-level silicon optical interconnects.Index Terms-Design for manufacturing, microring resonators, silicon-on-Insulator (SOI), wavelength-division multiplexing.

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“…As motivated earlier, a macrochip is a logically contiguous piece of photonically interconnected silicon that integrates CPUs, memory, and a system-wide interconnect [6]. It provides significant advantages in computational density, energy efficiency, bisection bandwidth, and reduced message latency over traditional integrated multichip systems.…”

Section: Review Of the Macrochipmentioning

confidence: 99%

Integration and Packaging of a Macrochip With Silicon Nanophotonic Links

Cunningham

Krishnamoorthy

et al. 2011

IEEE J. Select. Topics Quantum Electron.

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Abstract-The technologies associated with integration and packaging have a significant impact on the overall system. In this paper, we review a silicon photonic "macrochip" system and its associated packaging that will allow dense wavelengthdivision multiplexed optical links to be intimately integrated and co-manufactured with the switching electronics. For this to happen, we anticipate a number of integration and packaging advances.

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Computer Systems Based on Silicon Photonic Interconnects

Cited by 389 publications

References 53 publications

High-speed Ge photodetector monolithically integrated with large cross-section silicon-on-insulator waveguide

High-speed Ge photodetector monolithically integrated with large cross-section silicon-on-insulator waveguide

Fabrication-Tolerant Four-Channel Wavelength-Division-Multiplexing Filter Based on Collectively Tuned Si Microrings

Integration and Packaging of a Macrochip With Silicon Nanophotonic Links

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