Computer-Aided Design for VLSI Circuits

Newton,; Sangiovanni-Vincentelli, A.

doi:10.1109/mc.1986.1663204

Cited by 31 publications

(3 citation statements)

References 9 publications

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“…In this work, the CFD-ACE+ code [46] is used to simulate the plasma and a general purpose circuit simulator SPICE [50] is used to simulate the external circuit. The CFD-ACE+ solver calculates the transport of the charged and neutral particles and the electric field by solving the PDEs.…”

Section: Numerical Modelmentioning

confidence: 99%

DC negative corona discharge in atmospheric pressure helium: transition from the corona to the ‘normal’ glow regime

Hasan

Antao

Farouk

2014

Plasma Sources Sci. Technol.

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Direct current (dc) negative corona discharges in atmospheric pressure helium are simulated via detailed numerical modeling. Simulations are conducted to characterize the discharges in atmospheric helium for a pin plate electrode configuration. A self-consistent two-dimensional hybrid model is developed to simulate the discharges and the model predictions are validated with experimental measurements. The discharge model considered consists of momentum and energy conservation equations for a multi-component (electrons, ions, excited species and neutrals) gas mixture, conservation equations for each component of the mixture and state relations. A drift-diffusion approximation for the electron and the ion fluxes is used. A model for the external circuit driving the discharge is also considered and solved along with the discharge model. Many of the key features of a negative corona discharge, namely non-linear current-voltage characteristics, spatially flat cathode current density and glow-like discharge in the high current regime are displayed in the predictions. A transition to the 'normal' glow discharge from the corona discharge regime is also observed. The transition is identified from the calculated current-voltage characteristic curve and is characterized by the radial growth of the negative glow and the engulfment of the cathode wire.

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Section: Numerical Modelmentioning

confidence: 99%

DC negative corona discharge in atmospheric pressure helium: transition from the corona to the ‘normal’ glow regime

Hasan

Antao

Farouk

2014

Plasma Sources Sci. Technol.

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“…The problem with closed, highly integrated CAD-systems is their low flexibility. In [6] it is stated that: "it is essential that a CAD system be able to support a variety of design styles and adapt easily to new developments in these areas". The authors also conclude that an open tool-framework answers these purposes best.…”

Section: A Knowledge-based System In An Open Cadenvironmentmentioning

confidence: 99%

A knowledge-based approach to VLSI-design in an open CAD-environment

Alberts

Huijs

Mars

et al. 1989

Microprocessing and Microprogramming

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A knowledge-based approach is suggested to assist a designer in the increasingly complex task of generating VLSI-chips from abstract, high-level specifications of the system. The complexity of designing VLSI-circuits has reached a level where computer-based assistance has become indispensable. Not all of the design tasks allow for algorithmic solutions. AI techniques can be used, in order to support the designer with computer-aided tools for tasks not suited for algorithmic approaches. The approach described in this paper is based upon the underlying characteristics of VLSI design processes in general, comprising all stages of the design. A universal model is presented, accompanied with a recording method for the acquisition of design knowledge -strategic and task-specific -in terms of the design actions involved and their effects on the design itself. This method is illustrated by a simple design example: the implementation of the logical EXOR-component. Finally suggestions are made for obtaining a universally usable architecture of a knowledge-based system for VLSI-design. Characteristics of VLSI-designGiven a high-level, formal specification of the system, the designer of a VLSI-circuit is confronted with the problem of generating a description of the circuit that can be physically realized. Since this can not be done in a single design step, a stepwise refinement of the original description is carded out. For each design step the designer must choose among a set of alternative design actions suited for the situation. After each refinement verification of the results is needed and often some sort of optimization is performed. Depending on whether the results meet the necessary requirements, the designer will continue by selecting the next action or else he will have to reconsider the choices made. This cycle is repeated over and over, leading to a gradual refinement of the design.There are several constraints acting on the design process. On the one hand the technological and physical conditions constrain the possible design actions, as a consequence of the technology available and the characteristics of the silicon respectively. Secondly, there are a number of technical specifications that have to be met, like for example the maximum size of the final chip. The technological and physical implications are primarily bottom-up, whereas the techieal specifications work more top-down through the design process. So in effect, of only one the exact nature is known until they meet somewhere in the middle.In other words: the design process can be characterised as a complex search-process -through the intermediate design descriptions that are generated -under a number of constraints. The search is not for a single best solution, but for an acceptable compromise from a range of solutions that satisfy the requirements up to a certain degree. The complexity of this process is due to (among other things):a very large search-space, caused by the long trajectory from high-level system specification to low-level phys...

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“…The increase in VLSI circuit complexity has turned test generation into a major bottleneck in the design cycle. One way to tackle the complexity of .test generation for these circuits, is to usc a higher level of abstraction in the design description, thus reducing the amount of detail to be dealt with In this work, we assume that the design is described as a network of interconnccte"d functional blocks (e.g., adders, multiplexers, etc), as would be the case of designs using a library approach [1,2].…”

Section: Introductionmentioning

confidence: 99%

RIDDLE: a foundation for test generation on a high-level design description

Silberman

Spillinger

1991

IEEE Trans. Comput.

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We present a formal approach to the analysis of a VLSI design described at the high level, which produces information conducive to the acceleration cr I"" rcneration algorithms. This analysis yields as its main product, information which can be used to reduce the amount of effort expended during backtracing, hy guiding this process towards decisions (assignments) less likely to cause conflicts, and mmimizing the amount of work between backtracks. RIDDLE, an algorithm which performs this analysis in time linear in the number of signals, is introduced. Expcrimenta1 results for the special case of combinatorial gate level designs are also given. KeywordsBacktracing, design decomposition, hIgh level description, test generation.In the following, we take a backtracing-based test pattern generation algorithm for a high level design description [9], and we show how pre-processing of the design can improve the algorithm's performance. This pre-processing, pefformed by RIDDLE (Reconvergence-Independent Design Decomposition and I,abeling of Edges), generalizes and extends the concepts in FAN [5], LAYtP2 [6] and TOPS [7], so that they apply t

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Computer-Aided Design for VLSI Circuits

Cited by 31 publications

References 9 publications

DC negative corona discharge in atmospheric pressure helium: transition from the corona to the ‘normal’ glow regime

DC negative corona discharge in atmospheric pressure helium: transition from the corona to the ‘normal’ glow regime

A knowledge-based approach to VLSI-design in an open CAD-environment

RIDDLE: a foundation for test generation on a high-level design description

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