Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs

Wang, Xiaowei; Goyal, Vidushi; Yu, Jiecao; Bertacco, Valeria; Boutros, Andrew; Nurvitadhi, Eriko; Augustine, Charles; Iyer, Ravi; Das, Reetuparna

doi:10.1109/fccm51124.2021.00018

Cited by 14 publications

(10 citation statements)

References 24 publications

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“…al. proposed integrating the technology from Neural Cache into FPGA BRAMs to create Compute Capable BRAMs (CCB) [19]. The complexity associated with the reduction in voltage required to ensure robustness when activating multiple wordlines makes this architecture not very practical.…”

Section: B Compute-in-memorymentioning

confidence: 99%

“…A processing element (PE) is added below each column. This is similar to the architecture used in [3], [23] and [19]. During physical design/implementation, PEs should be laid out so that they pitch-match with the SRAM cells (and sense amplifiers and write drivers) for a bitline pair (BL and BLB).…”

Section: Sense Amplifiersmentioning

confidence: 99%

“…A different sequence of instructions is all that's required to compute in a different precision. The sequences for fixed-point addition and multiplication were explained in Section III-E. CoMeFa RAMs can natively support floating point precisions as well, as opposed to CCB [19]. We adapt the floating point algorithms for addition and multiplication from FloatPIM [9].…”

Section: G Variable Precision Supportmentioning

confidence: 99%

Section: Implementation Detailsmentioning

confidence: 99%

“…CCB: The implementation of CCB [19] is based on a BRAM with 128x128 geometry. The area overhead for the CCB block evaluated in [19] does not include the area of the additional sense amplifiers and write drivers. In our re-implementation of CCB, the total area overhead comes out to be 872.64 um 2 , which is a 16.8% increase at the block level and 2.5% at the chip level in the Arria-10-like FPGA used in this study.…”

Section: Implementation Detailsmentioning

confidence: 99%

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CoMeFa: Compute-in-Memory Blocks for FPGAs

Arora¹,

Anand²,

Borda³

et al. 2022

Preprint

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Block RAMs (BRAMs) are the storage houses of FPGAs, providing extensive on-chip memory bandwidth to the compute units implemented using Logic Blocks (LBs) and Digital Signal Processing (DSP) slices. We propose modifying BRAMs to convert them to CoMeFa (Compute-In-Memory Blocks for FPGAs) RAMs. These RAMs provide highly-parallel computein-memory by combining computation and storage capabilities in one block. CoMeFa RAMs utilize the true dual port nature of FPGA BRAMs and contain multiple programmable singlebit bit-serial processing elements. CoMeFa RAMs can be used to compute in any precision, which is extremely important for evolving applications like Deep Learning. Adding CoMeFa RAMs to FPGAs significantly increases their compute density. We explore and propose two architectures of these RAMs: CoMeFa-D (optimized for delay) and CoMeFa-A (optimized for area). Compared to existing proposals, CoMeFa RAMs do not require changing the underlying SRAM technology like simultaneously activating multiple rows on the same port, and are practical to implement. CoMeFa RAMs are versatile blocks that find applications in numerous diverse parallel applications like Deep Learning, signal processing, databases, etc. By augmenting an Intel Arria-10-like FPGA with CoMeFa-D (CoMeFa-A) RAMs at the cost of 3.8% (1.2%) area, and with algorithmic improvements and efficient mapping, we observe a geomean speedup of 2.5x (1.8x), across several representative benchmarks. Replacing all or some BRAMs with CoMeFa RAMs in FPGAs can make them better accelerators of modern compute-intensive workloads.

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Section: B Compute-in-memorymentioning

confidence: 99%

Section: Sense Amplifiersmentioning

confidence: 99%

Section: G Variable Precision Supportmentioning

confidence: 99%

Section: Implementation Detailsmentioning

confidence: 99%

Section: Implementation Detailsmentioning

confidence: 99%

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CoMeFa: Compute-in-Memory Blocks for FPGAs

Arora¹,

Anand²,

Borda³

et al. 2022

Preprint

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An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration

et al. 2023

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FPGA-based acceleration is considered a promising approach to improve the performance and power efficiency of Deep Neural Network (DNN) inference tasks. However, mapping a DNN onto an FPGA is not trivial. To make this easier, various automation frameworks have been proposed. Among them, FINN and Vitis AI, both developed by Xilinx, are two key players. They represent two different philosophies in designing FPGA-based DNN accelerators: dataflow-style and overlay-style architectures. Dataflow architectures are generally expected to provide better performance and power efficiency but have a major drawback in that they scale very poorly to the size of the target DNN. Advanced frameworks like FINN alleviate this drawback by transforming the target DNN into operations that can be time-multiplexed on fewer hardware resources. This approach, however, is challenging because of the difficulty in transforming the target DNN and raises a question as to whether the generated dataflow architectures retain a significant advantage over overlay architectures in terms of performance and power efficiency. This paper aims to clarify it by conducting an in-depth exploration of FINN and Vitis AI. For this purpose, we extend the FINN's development flow to be able to use the same target hardware and DNN model to evaluate each framework. We demonstrate the effectiveness of the FPGA-based acceleration by providing a comparison with two reference platforms: an NVIDIA Jetson Nano Developer Kit with a similar power budget to our target FPGA hardware, and a high-performance desktop computer with an Intel Core i7-11700K CPU. The results show that despite the use of the time-multiplexing approach, the FINN-based accelerator can still outperform the Vitis-AI-based accelerator by a significant margin, 8.4x in terms of latency, 3.0x in terms of throughput, and 3.3x in terms of power efficiency. The outcome of the comparison with the NVIDIA Jetson Nano Developer Kit and the desktop computer is also overwhelmingly favorable to the FINN-based accelerator. This indicates that, even in the case of using automation frameworks, DNN accelerators on FPGAs can still yield significant performance and power efficiency gains compared with GPUs and CPUs.

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