CoMeFa: Compute-in-Memory Blocks for FPGAs

Arora, Aman; Anand, Tanmay; Borda, Aatman; Sehgal, Rishabh; Hanindhito, Bagus; Kulkarni, Jaydeep P.; John, Lizy K.

doi:10.1109/fccm53951.2022.9786179

Cited by 11 publications

(4 citation statements)

References 23 publications

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“…Binary Neural Network (1b) [30,31] customises and constrains the training process to achieve LUT compatibility, TLMAC derives optimised LUT initialisations from state-of-the-art quantised models directly. function as both a compute engine and traditional memory [3,7,32]. However, these circuits were largely tested through simulations.…”

Section: Routing Optimisationmentioning

confidence: 99%

“…To implement bit-serial operations close to the memory port, it had to add logic for serialisation and enhance memory cell access. CoMeFa [3] enhances both ports of dual-port BRAMs with write drivers and sense amplifiers. Circuits for processing elements are proposed that write input and read output data.…”

Section: Related Research 21 Computing-in-memory On Fpgasmentioning

confidence: 99%

“…Circuits for processing elements are proposed that write input and read output data. Their bit-serial computation principle has also been applied to deep learning workloads [4]. BRAMAC [7] overcomes some of the previous implementation and performance restrictions by executing operations on separate dummy BRAMs.…”

Section: Related Research 21 Computing-in-memory On Fpgasmentioning

confidence: 99%

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Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic

Gerlinghoff,

Choong,

Goh

et al. 2024

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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Recent advancements in neural network quantisation have yielded remarkable outcomes, with three-bit networks reaching state-ofthe-art full-precision accuracy in complex tasks. These achievements present valuable opportunities for accelerating neural networks by computing in reduced precision. Implementing it on FPGAs can take advantage of bit-level reconfigurability, which is not available on conventional CPUs and GPUs. Simultaneously, the high data intensity of neural network processing has inspired computing-in-memory paradigms, including on FPGA platforms. By programming the effects of trained model weights as lookup operations in soft logic, the transfer of weight data from memory units can be avoided, alleviating the memory bottleneck. However, previous methods face poor scalability -the high logic utilisation limiting them to small networks/sub-networks of binary models with low accuracy. In this paper, we introduce Table Lookup Multiply-Accumulate (TLMAC) as a framework to compile and optimise quantised neural networks for scalable lookup-based processing. TLMAC clusters and maps unique groups of weights to lookupbased processing elements, enabling highly parallel computation while taking advantage of parameter redundancy. Further place and route algorithms are proposed to reduce LUT utilisation and routing congestion. We demonstrate that TLMAC significantly improves the scalability of previous related works. Our efficient logic mapping and high degree of reuse enables entire ImageNet-scale quantised models with full-precision accuracy to be implemented using lookup-based computing on one commercially available FPGA.

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Section: Routing Optimisationmentioning

confidence: 99%

Section: Related Research 21 Computing-in-memory On Fpgasmentioning

confidence: 99%

Section: Related Research 21 Computing-in-memory On Fpgasmentioning

confidence: 99%

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Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic

Gerlinghoff,

Choong,

Goh

et al. 2024

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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“…The new developments in the programmability of FPGAs allow these devices to abandon their original niche and be used to solve general-purpose problems. In particular, several recent works on FPGAs focus on the implementation of numerical linear algebra (NLA) kernels [4][5][6], which are a crucial component of a myriad of applications. However, most works focus on dense NLA [7][8][9], as well as other algorithms more suited for FPGAs such as image processing [10,11], machine learning [12], etc.…”

Section: Introductionmentioning

confidence: 99%

Optimizing the Performance of the Sparse Matrix–Vector Multiplication Kernel in FPGA Guided by the Roofline Model

Favaro,

Dufrechou,

Oliver

et al. 2023

Micromachines

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The widespread adoption of massively parallel processors over the past decade has fundamentally transformed the landscape of high-performance computing hardware. This revolution has recently driven the advancement of FPGAs, which are emerging as an attractive alternative to power-hungry many-core devices in a world increasingly concerned with energy consumption. Consequently, numerous recent studies have focused on implementing efficient dense and sparse numerical linear algebra (NLA) kernels on FPGAs. To maximize the efficiency of these kernels, a key aspect is the exploration of analytical tools to comprehend the performance of the developments and guide the optimization process. In this regard, the roofline model (RLM) is a well-known graphical tool that facilitates the analysis of computational performance and identifies the primary bottlenecks of a specific software when executed on a particular hardware platform. Our previous efforts advanced in developing efficient implementations of the sparse matrix–vector multiplication (SpMV) for FPGAs, considering both speed and energy consumption. In this work, we propose an extension of the RLM that enables optimizing runtime and energy consumption for NLA kernels based on sparse blocked storage formats on FPGAs. To test the power of this tool, we use it to extend our previous SpMV kernels by leveraging a block-sparse storage format that enables more efficient data access.

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BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs

Chen

Abdelfattah

2023

2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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CoMeFa: Compute-in-Memory Blocks for FPGAs

Cited by 11 publications

References 23 publications

Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic

Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic

Optimizing the Performance of the Sparse Matrix–Vector Multiplication Kernel in FPGA Guided by the Roofline Model

BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs

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