Computational image sensor for on sensor compression

Aizawa, Kiyoharu; Egi, Y.; Hamamoto, Takayuki; Hatori, Mitsutoshi; Abe, Masahide; Maruyama, Hirotaka; Otake, Hiroshi

doi:10.1109/16.628829

Cited by 41 publications

(9 citation statements)

References 1 publication

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“…This paper presents a high-speed CMOS image sensor integrating parallel image compression circuits for high-speed image data transfer with limited output bus width. This is the first attempt to integrate an image compression function on a high-speed CMOS image sensor for increasing the effective data rate, through a few type of image sensor chips with data compression function using analog-domain operation have been reported [5] [6]. Figure 1 shows the proposed architecture of high-speed CMOS image sensor with parallel image compression circuits.…”

Section: Introductionmentioning

confidence: 97%

A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits

Nishikawa

Kawahito

Furuta

et al. 2007

2007 IEEE Custom Integrated Circuits Conference

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This paper presents a high-speed CMOS image sensor with on-chip parallel image compression circuits. The chip consists of a pixel array, an A/D converter array with noise canceling function and an image compression processing element array and buffer memories. The image compression processing element is implemented with a 4×4 point Discreate Cosine Transform(DCT) and a modified zigzag scanner with 4 blocks. A prototype high-speed CMOS image sensor integrating the image compression circuits is implemented based on 1-poly 5-metal 0.25-µm CMOS technology. Image encoding using the implemented parallel image compression circuits to the image captured by the high-speed image sensor is successfully performed at 3,000[frame/s].

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Section: Introductionmentioning

confidence: 97%

A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits

Nishikawa

Kawahito

Furuta

et al. 2007

2007 IEEE Custom Integrated Circuits Conference

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“…Monte Carlo simulations of the entire vector quantizer in Spectre with parameters from 0.35 μm technology have shown that it is quite robust to mismatch variations typical in CMOS fabrication technologies. For recent references on focal-plane implementation of image processing algorithms, we refer the reader to [1,2,3] (on general image processing) and to [4,5,6] (on scalar image coding). We consider only gray-level images.…”

Section: Introductionmentioning

confidence: 99%

Analog hardware implementation of a vector quantizer for focal-plane image compression

Haas

Gomes

Petraglia

2008

Proceedings of the 21st Annual Symposium on Integrated Circuits and System Design

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We propose the use of a low-complexity vector quantizer for coding data vectors at the focal plane of CMOS image sensors, directly from analog pixels samples prior to A/D conversion. To be suitable for focal-plane image compression applications, the encoder must have a very low transistor count. Without considering the implementation errors in DPCM preprocessing of the image data, a test image is compressed by the proposed vector quantizer with peak signal-to-noise ratio around 26 dB at 0.73 bpp. The vector quantizer requires 145 transistors for each block of 4 × 4 pixels, and Monte Carlo simulation results in Cadence/Spectre led to the same image compression results that had been achieved in theoretical predictions.

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“…Finally, this approach can consume less power than a multi-chip image compression system. Most image compression processing circuits are integrated outside of the sensor array [2]- [6]. Rows or blocks of image data need to be sequentially scanned onto the external compression processing circuit.…”

Section: Introductionmentioning

confidence: 99%

A CMOS Front-End for a Lossy Image Compression Sensor

Lin

Hoffman

Leon

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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A CMOS image sensor has been designed to perform the front-end image decomposition in a Prediction-SPIHT image compression scheme. The prediction circuitry based on charge sharing is integrated inside the sensor array to perform a 3-level image decomposition. A CMOS test chip has been prototyped and tested. The test results justify the pixel design and demonstrate that lossy prediction based focal plane image compression can be realized inside the sensor pixel array to achieve a high frame rate but with much less data readout volume. Also, the sensor can be used to achieve comparable compression performance with much lower computational complexity compared to 2D discrete wavelet transform (DWT) based image compression.

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Computational image sensor for on sensor compression

Cited by 41 publications

References 1 publication

A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits

A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits

Analog hardware implementation of a vector quantizer for focal-plane image compression

A CMOS Front-End for a Lossy Image Compression Sensor

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