Computation Sharing Programmable FIR Filter for Low-Power and High-Performance Applications

Efficient realization of reconfigurable FIR filter using the new coefficient representation

“…2 (b)) are designed and synthesized on Altera Stratix Family FPGA device, EP1S10B672C6, utilizing Quartus II software. To compare the complexity and hardware usage of proposed reconfigurable FIR filters with previously reported works, two other reconfigurable filters are designed and synthesized based on the architectures of [6] (4 bit subcoefficients) and [7] (3 bit subcoeffi- Table I. Comparison of FPGA resources usage in the conventional [6,7] and proposed approaches cients).…”

“…To compare the complexity and hardware usage of proposed reconfigurable FIR filters with previously reported works, two other reconfigurable filters are designed and synthesized based on the architectures of [6] (4 bit subcoefficients) and [7] (3 bit subcoeffi- Table I. Comparison of FPGA resources usage in the conventional [6,7] and proposed approaches cients). The hardware usage of proposed 4-bit BSS filter has been compared with the architecture of [6] in Table I.…”

“…In programmable and reconfigurable applications, the filter coefficients are not fixed and it is not easy to find the common subexpressions for newly applied coefficients. Several implementation approaches have been proposed in [3,4,5,6,7] for reconfigurable and programmable FIR filters. In [3] a fully programmable multiply accumulate (MAC) based filter processor has been proposed which is suffering from large delay of long datapath, large area and power requirements.…”

“…An interesting CSD based digit reconfigurable FIR filter architectures have been proposed in [4] and [5], where its area and power consumption are also high. Two other efficient reconfigurable FIR filter implementation approaches have been presented in [6] and [7]. These works have been focused on the implementing FIR filter by partitioning the filter coefficient into fixed groups (sub-coefficients or named alphabet in [6]) and pre-computing the products of input data with these constant fixed subcoefficients.…”

“…Two other efficient reconfigurable FIR filter implementation approaches have been presented in [6] and [7]. These works have been focused on the implementing FIR filter by partitioning the filter coefficient into fixed groups (sub-coefficients or named alphabet in [6]) and pre-computing the products of input data with these constant fixed subcoefficients. These partial products are distributed inside the chip instead of the input data and processed by each tap's process element (PE) to compose the desired coefficient multiplication.…”