2011
DOI: 10.1587/elex.8.902
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Efficient realization of reconfigurable FIR filter using the new coefficient representation

Abstract: Abstract:In this paper, efficient reconfigurable finite-impulse response (FIR) filter architecture is presented based on a new coefficient representation method. The proposed binary signed subcoefficient method increases the common subexpressions and decrease the hardware usage and complexity. FPGA synthesis results of the designed two reconfigurable FIR filter architectures show that 33% and 27% reductions in the resources usage are achievable over the previously reported two state of the art reconfigurable a… Show more

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Cited by 5 publications
(1 citation statement)
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“…Area efficient FIR filters using Canonic Signed Digit (CSD), Common Sub Expression (CSE) and Distributed Arithmetic (DA) [23,24,25,26] offers a better filter design solution compared to multiply and accumulate-based approach [27,28,29,30,31].…”
Section: Introductionmentioning
confidence: 99%
“…Area efficient FIR filters using Canonic Signed Digit (CSD), Common Sub Expression (CSE) and Distributed Arithmetic (DA) [23,24,25,26] offers a better filter design solution compared to multiply and accumulate-based approach [27,28,29,30,31].…”
Section: Introductionmentioning
confidence: 99%