Comprehensive Thermo-Mechanical Stress Analyses and Underfill Selection of Large Die Flip Chip Ball Grid Array

Hsieh, Ming-Che; Lee, Chien Chen; Hung, Li Chiun

doi:10.1109/tcpmt.2012.2232712

Cited by 10 publications

(2 citation statements)

References 10 publications

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“…From literature [1], that solder bumps were always subjected to strain and stress and eventually initiated/propagated fatigue cracks in solder bumps due to the constraints of thermal expansion was wellknown. Additionally, the IMC was usually formed on the top of Cu pad and caused the interfaces to become brittle to sustained stresses.…”

Section: Reliability Assessmentmentioning

confidence: 99%

Reliability behaviors of an exposed die FCCSP on a substrate with ultra-low CTE laminate material

Cheng

Zhan

Fun

et al. 2015

2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)

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Flip chip package has been reported to be an ideal package solution of high bandwidth devices because of a lower power loss and a short transmission route of signal. However, some failure modes such as solder joint crack, delamination of substrate or low-k delamination within IC were often found after reliability verification. One of the key factors of failure is attributed to the mismatch of CTE values between Si chip (4 ppm) and substrate (tens ppm), and ultralow CTE laminate materials are really needed to improve the reliability to automotive-level. In this study, a 1/2/1 substrate with a dimension of 12 mm  12 mm  0.22 mm was made by laminating low-CTE or low-Young's modulus prepreg on a 100 m thick core. FCCSPs with four types of core and PP-like build-up material were assembled and tested to understand the effect of selected material properties on the reliability response. The simulation results revealed that the effects of selected material properties such as low CTE and low Young's modulus on the warpage behavior were not apparent. Also, the warpage of the tested FCCSPs might not be the dominated factor to affect the reliability performance. Simulate induced stress/strain during reliability test would be the major factor to decide the reliability performance of solder joints. The FCCSP having the highest maximum strain within the solder joints would fail after thermal cycling test. Low CTE material could reduce simulate maximum strain within the solder joints. In addition, the effect of low CTE seemed to be more prominent than that of low Young's modulus on simulate maximum strain value. By numerical analysis and reliability test, beneficial effect of prepreg with low-CTE and low Young's modulus on the reliability response had been confirmed.

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Section: Reliability Assessmentmentioning

confidence: 99%

Reliability behaviors of an exposed die FCCSP on a substrate with ultra-low CTE laminate material

Cheng

Zhan

Fun

et al. 2015

2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)

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show abstract

“…1. It is well known that with the use of UBM on the solder balls can enhance the package reliability [14]- [16]. However, the failure mode of intermetallic compound (IMC) crack on UBM and/or PCB Cu pad was observed in the 2P2M WLCSP structure during board level reliability (BLR) thermal cycling test (TCT) [2], [7], [17], [18], which suggested that the phenomenon of solder crack is still a concern even with the adopted UBM structure.…”

Section: Introductionmentioning

confidence: 99%

Finite Element Analyses for Critical Designs of Low-Cost Wafer-Level Chip Scale Packages

Hsieh¹

2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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With the advantages of high performance and low cost, the wafer-level chip scale package (WLCSP) is widely used in integrated circuit fabrication today with rapidly growing demand in the semiconductor packaging industry. As WLCSP moves toward thinner, smaller, lower cost, and fine-pitch package designs to meet the increasing requirements of electronic products, a lot of challenges need to be overcome. The most important challenge is preventing failure and enhancing package reliability. To understand the mechanical behaviors of WLCSP, comprehensive finite-element analyses (FEAs) for various WLCSP structures, including the general design with one under-bumpmetallurgy layer, one redistribution layer (RDL), and two polymer layers on a passivated wafer (called 2P2M WLCSP in this paper, which means that there are two polymer layers and two metal layers on the passivated wafer), the low-cost designs of 2P1M WLCSP (with two polymer layers and only one RDL on a passivated wafer) as well as 1P1M WLCSP (with only one polymer layer and one RDL on a passivated wafer) were carried out. Different parameters in WLCSP were investigated to look for critical factors that impact the corresponding stresses. Moreover, the board level reliability thermal cycling test that followed JEDEC standard was used, which suggested that the solder cracks were observed mostly near the intermetallic compound layer in WLCSP structures and aligned with the FEA results. Hence, by employing reliable modeling, not only can the critical factors that affect the stress responses be obtained but also can the proper parameters to provide the best reliability in WLCSP be determined. This paper offers a good reference and can effectively serve as design guidelines in cases of significant factor selection analyses on WLCSP designs.Index Terms-Finite-element analysis (FEA), parametric study, stress analysis, thermal cycling test (TCT), wafer-level chip scale package (WLCSP).

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Development and optimization of the laser-assisted bonding process for a flip chip package

2019

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Comprehensive Thermo-Mechanical Stress Analyses and Underfill Selection of Large Die Flip Chip Ball Grid Array

Cited by 10 publications

References 10 publications

Reliability behaviors of an exposed die FCCSP on a substrate with ultra-low CTE laminate material

Reliability behaviors of an exposed die FCCSP on a substrate with ultra-low CTE laminate material

Finite Element Analyses for Critical Designs of Low-Cost Wafer-Level Chip Scale Packages

Development and optimization of the laser-assisted bonding process for a flip chip package

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