Comprehensive Study of the Electron Scattering Mechanisms in 4H-SiC MOSFETs

Uhnevionak, Viktoryia; Burenkov, A.; Strenger, Christian; Ortiz, Guillermo P.; Bedel-Pereira, Eléna; Mortet, Vincent; Cristiano, Fuccio; Bauer, Anton J.; Pichler, P.

doi:10.1109/ted.2015.2447216

Cited by 59 publications

(41 citation statements)

References 23 publications

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“…However, differently from Si, where

versus

curves merge with each other when surface roughness scattering becomes the dominant regime, this universal behavior is not visible for 4H-SiC in Figure 6 . This is consistent with earlier studies on 4H-SiC n-channel MOSFETs [ 14 , 23 , 24 , 27 , 28 ]. Perhaps for a single 4H-SiC MOSFET, the measurable range of

is not large enough before the breakdown of the gate dielectric to observe the merging of

at higher

, and a larger range of measurements using devices with different substrate doping is necessary, as reported in [ 24 ].…”

Section: Resultssupporting

confidence: 93%

Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis

Das

Zheng²,

Ahyi³

et al. 2022

Materials

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The channel conduction in 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs) are highly impacted by charge trapping and scattering at the interface. Even though nitridation reduces the interface trap density, scattering still plays a crucial role in increasing the channel resistance in these transistors. In this work, the dominant scattering mechanisms are distinguished for inversion layer electrons and holes using temperature and body-bias-dependent Hall measurements on nitrided lateral 4H-SiC MOSFETs. The effect of the transverse electric field (Eeff) on carrier mobility is analyzed under strong inversion condition where surface roughness scattering becomes prevalent. Power law dependencies of the electron and hole Hall mobility for surface roughness scattering are determined to be Eeff−1.8 and Eeff−2.4, respectively, analogous to those of silicon MOSFETs. Moreover, for n-channel MOSFETs, the effect of phonon scattering is observed at zero body bias, whereas in p-channel MOSFETs, it is observed only under negative body biases. Along with the identification of regimes governed by different scattering mechanisms, these results highlight the importance of the selection of substrate doping and of Eeff in controlling the value of channel mobility in 4H-SiC MOSFETs.

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“…However, differently from Si, where

versus

is not large enough before the breakdown of the gate dielectric to observe the merging of

at higher

, and a larger range of measurements using devices with different substrate doping is necessary, as reported in [ 24 ].…”

Section: Resultssupporting

confidence: 93%

Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis

Das

Zheng²,

Ahyi³

et al. 2022

Materials

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“…Obviously, for Hall measurements, special test patterns must be designed (i.e., Hall bars in the MOSFET channel). Moreover, the accurateness of this method is correlated to the knowledge of the Hall scattering factor [43]. Recently, Hall measurements have been used by Hatakeyama et al [33] to determine the total amount of the trapped and free carriers in the channel of 4H-SiC MOSFETs subjected to different NO treatments, and their results are reported in Table 1.…”

Section: Processmentioning

confidence: 99%

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

2019

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This paper gives an overview on some state-of-the-art characterization methods of SiO2/4H-SiC interfaces in metal oxide semiconductor field effect transistors (MOSFETs). In particular, the work compares the benefits and drawbacks of different techniques to assess the physical parameters describing the electronic properties and the current transport at the SiO2/SiC interfaces (interface states, channel mobility, trapping phenomena, etc.). First, the most common electrical characterization techniques of SiO2/SiC interfaces are presented (e.g., capacitance- and current-voltage techniques, transient capacitance, and current measurements). Then, examples of electrical characterizations at the nanoscale (by scanning probe microscopy techniques) are given, to get insights on the homogeneity of the SiO2/SiC interface and the local interfacial doping effects occurring upon annealing. The trapping effects occurring in SiO2/4H-SiC MOS systems are elucidated using advanced capacitance and current measurements as a function of time. In particular, these measurements give information on the density (~1011 cm−2) of near interface oxide traps (NIOTs) present inside the SiO2 layer and their position with respect to the interface with SiC (at about 1–2 nm). Finally, it will be shown that a comparison of the electrical data with advanced structural and chemical characterization methods makes it possible to ascribe the NIOTs to the presence of a sub-stoichiometric SiOx layer at the interface.

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“…To establish the simulation model of the device at high temperatures, various temperature-related physical models used in the device module were designed in this paper. It includes the bandgap model, incomplete ionization model, mobility model, and interface charge model (synopsys inc, 2021; Arora et al , 1982; Hatakeyama et al , 2003; Lombardi et al , 1988; Uhnevionak et al , 2015; Canali et al , 1975). Related parameters of 4H-SiC were applied in the bandgap model, incomplete ionization model, mobility model.…”

Section: Sentaurus Tcad Modelmentioning

confidence: 99%

Study on high temperature model based on the n-Channel planar 4H-SiC MOSFET

Tang

Pu³

et al. 2021

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Purpose To use the 4H-SiC material in integrated circuits for high temperature application, an accurate and simple circuit model of n-channel planar 4H-SiC MOSFET is required. Design/methodology/approach In this paper, a SPICE model of n-channel planar 4H-SiC MOSFET was built based on the device simulation results and measurement results. Firstly, a device model was simulated with Sentaurus TCAD, with measured parameters from fabricated planar 4H-SiC MOSFET previously. Then the device simulation results were analyzed and parameters for SPICE models were extracted. With these parameters, an accurate SPICE model was built and simulated. Findings The SPICE model exhibits the same performance as the measured results with different environment temperatures. The simulation results indicate that the maximum fitting error is 0.22 mA (7.33% approximately) at 200 °C. A common-source amplifier with this model is also simulated and the simulated gain is stable at different environment temperatures. Originality/value This paper provides a reliable modeling method for n-Channel Planar 4H-SiC MOSFET and reference value for the design of 4H-SiC high temperature integrated circuit.

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Comprehensive Study of the Electron Scattering Mechanisms in 4H-SiC MOSFETs

Cited by 59 publications

References 23 publications

Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis

Study of Carrier Mobilities in 4H-SiC MOSFETS Using Hall Analysis

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

Study on high temperature model based on the n-Channel planar 4H-SiC MOSFET

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