Comprehensive Study of ESD Design Window Scaling Down to 7nm Technology Node

Dong, Aihua; Xiong, Jin; Mitra, Subhasish; Liang, Wei; Gauthier, Robert; Loiseau, Alain

doi:10.23919/eos/esd.2018.8509689

Cited by 18 publications

(2 citation statements)

References 6 publications

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“…15 (b) shows the node voltage waveforms of the ESD/EOS protection circuit in the entire 100 ns TLP simulation. The experimental results show that the gate oxide breakdown voltage of the advanced bulk MOSFET under 100 ns TLP test is over 3 V [23], indicating that the proposed circuit can protect the devices. VDD first rises to about 2.4 V at 10 ns, and then gradually falls.…”

Section: Proposed Protection Circuit Under Esd Eventmentioning

confidence: 96%

TFET-Based Voltage Detector: Proposal and Investigation

Yang

Gao

2020

IEEE Access

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In this paper, a tunnel field-effect transistor (TFET)-based voltage detector is proposed and its electrical characteristics are investigated using technology computer-aided design (TCAD) simulation. The operating principle of the proposed voltage detector is explained and possible applications in electrical overstress (EOS) and electrostatic discharge (ESD) protection are explored. Moreover, the impact of the key parameters on device performance is also discussed. The simulation results show that the proposed TFET-based voltage detector has a low leakage current and high detection sensitivity under EOS events compared to traditional diode-based detectors. With an additional nMOSFET capacitor, the proposed circuit can also be used for ESD protection. INDEX TERMS Band-to-band tunneling (BTBT); electrical overstress (EOS); electrostatic discharge (ESD); tunnel field-effect transistor (TFET); voltage detector.

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Section: Proposed Protection Circuit Under Esd Eventmentioning

confidence: 96%

TFET-Based Voltage Detector: Proposal and Investigation

Yang

Gao

2020

IEEE Access

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“…burst. However, on account of the shrunken design window and smaller effective silicon volume for thermal dispassion, the electrostatic discharge (ESD) problem is more serious and continues to attract the interest of researchers [1].…”

Section: Introductionmentioning

confidence: 99%

All-HKMG-bounded SCR for advanced ESD protection in 14 nm FinFET technology

Du¹,

Xie²,

Wang³

et al. 2022

Semicond. Sci. Technol.

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In this paper, a novel all-high-K metal gate (HKMG)-bounded silicon-controlled rectifier (AHBSCR) is proposed for advanced electrostatic discharge (ESD) protection in FinFET processes. Depart from its prior arts, in AHBSCR, both the main SCR path and the triggering diode path are placed along the Fin direction, and all active areas are bounded by HKMG, thus expressing superior conduction capability under various ESD stresses and a more compact silicon footprint. Experimental results show that the proposed AHBSCR owns a suitable snapback window of 1.1 V–1.6 V, a fast turn-on speed of only 400 ps, an extreme low leakage current of less than 100 pA@-1 V as well as a figure of merit of 24.3 mA fF−1, indicating it is competent to replace the conventional FinFET diodes in rail-based ESD network to further improve the efficiency of ESD protection.

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