Comprehensive CD uniformity control across lithography and etch

Zhang, Qiaolin; Tang, Cherry; Hsieh, Tony; Maccrae, Nick; Singh, Bhanwar; Poolla, Kameshwar; Spanos, Costas J.

doi:10.1117/12.601087

Cited by 13 publications

(7 citation statements)

References 6 publications

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“…This is an example of a swing curve with minima and maxima. Wafer numbers 1,2,4, 6,8,10,12,14,16,18,20 and 22 are in first set while wafer 5,7,9,11,13,15,17,19,21,and 23 are in second set. Wafer number 24 is exposed and developed first to find out the center exposure so that the clearing points are in the middle of the 20 by 10 matrix.…”

Section: Methodsmentioning

confidence: 99%

“…Improvements to CD uniformity have been made through optimization of various lithography sequences. They include die-to-die exposure dose optimization [2], focus control [3], grid size adjustment for optical proximity correction [4], writing a multitude of shading elements inside the mask to adjust wafer level CD uniformity [5], and post-exposure bake temperature profile optimization by adjusting heater power in a multi-zone controlled bake plate [6][7][8]. Photoresist thickness variation is one of the major contributors of CD variations [9].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology

Adam

Hashim

2012

2012 International Conference on Statistics in Science, Business and Engineering (ICSSBE)

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The swing curve is depending on the rotation speed of the spinner and the thickness of the photoresist. The thickness should be thick enough to prevent the unexposed area from being etched. It is also need to be uniform so that the image of the pattern to be developed later is in focus at all points on the resist surface. The variation of the photoresist thickness will impact the overall yield of the devices. In this respect, the photoresist thickness needs to be characterized carefully. Therefore, an experiment was set up to determine the right thickness and exposure time to control the critical dimension of the pattern. Photoresist coater and stepper are the main equipment used in this experiment. Positive photoresist is utilized as a pattern transfer medium and elipsometer is employed for film thickness measurement. 24 wafers are used in this experiment. The wafers are separated into 2 sets, each set which consists of 12 wafers have all the thickness variation. This to test the effect of standing resist before exposure and development to the dose-to-clear. The first set is coated, exposed and development. However, the second set is exposed and developed two days after being coated. After the wafer went through the standard cleaning procedure, the wafers were then coated using standard recipes which the spin speed ranging from 6500 to 7600 rpm in 100 rpm incremental with the designated rpm fro 1.2 µm photoresist thicknesses is in the middle. Subsequently, the photoresist thickness of each wafer is measured using elipsometer. Then, the exposure process is done by creating job that will expose the wafers in 20 by 10 arrays of small squares of open field with size 2x2 mm. The exposure is done in such a way where the exposure time will step up to the right and step down to the left from the center after each column. The center of the exposure energy time/step is 240/5. Then the graph is plotted to see the different. From the results we obtained that the minima for the dose-to-clear is at 7200 rpm where the thickness is 1.22 µm. whereby the first set and the second set of wafers produce a slight variation in clearing point.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology

Adam

Hashim

2012

2012 International Conference on Statistics in Science, Business and Engineering (ICSSBE)

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“…In addition, the gate CD prediction model (1) can predict the CD distribution in a wafer. Therefore, FF control in the lithography process will further reduce the CD variation across a wafer by using the shot-to-shot control of the exposure dose or temperature distribution of the hot plate at the postexposure bake, and so on [33].…”

Section: Lot-to-lot Ff Experimentsmentioning

confidence: 99%

Gate CD Control Considering Variation of Gate and STI Structure

Kurihara

Tanaka

Izawa

et al. 2007

IEEE Trans. Semicond. Manufact.

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We developed a fab-wide advanced process control system to control the critical dimension (CD) of gate electrode length in semiconductors. We also developed a model equation that predicts the gate CD by considering the structures of gate electrode and shallow trench isolation. This prediction model was also used to perform a factor analysis of gate CD variation. The effectiveness of the model in controlling feedforward was evaluated by both simulation and experiment. The CD variation of the wafers was improved from 8.9 nm in its 3 sigma without control to 3.5 nm with lot-to-lot feedforward control.

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“…Rule based OPC is being augmented with model based OPC and RETs are becoming more and more aggressive 1 . Advanced process control is leading to better predictability and various compensation techniques that aim at canceling out systematic variations 2,3 . These three techniques serve as precursors to Design for Manufacturing or DFM, where the objective is to increase yield and make OPC and RET more effective.…”

Section: Introduction/backgroundmentioning

confidence: 99%

Platform for collaborative DFM

2006

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A Process/Device/Design framework called the Parametric Yield Simulator is proposed for predicting circuit variability based on circuit design and a set of characterized sources of variation. In this simulator, the aerial image of a layout is simulated across a predefined process window and resulting non-idealities in geometrical features are communicated through to circuit simulators, where circuit robustness and yield can be evaluate in terms of leakage and delay variability. The purpose of this simulator is to identify problem areas in a layout and quantify them in terms of delay and leakage in a manner in which designers and process engineers can collaborate together on an optimal solution to the problem. The Parametric Yield Simulator will serve as a launch pad for collaborative efforts between groups in different disciplines that are looking at variability and yield. Universities such as Berkeley offer a great advantage in exploring innovative approaches as different centers of key expertise exist under one roof. For example a complementary set of characterization and validation experiments has also been designed and in a collaborative study is being executed at Cypress semiconductor on a 65nm NMOS process flow. This unique opportunity of having access to a cutting edge process flow with relatively high transparency has led to a new set of experiments with contributions from six different students in circuit design, process engineering, and device physics. Collaborative efforts with the device group have also led to a new electrical linewidth metrology methodology using enhanced transistors that could prove useful for process characterization.

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Comprehensive CD uniformity control across lithography and etch

Cited by 13 publications

References 6 publications

Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology

Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology

Gate CD Control Considering Variation of Gate and STI Structure

Platform for collaborative DFM

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Comprehensive CD uniformity control across lithography and etch

Cited by 13 publications

References 6 publications

Statistical parameter evaluation for swing curves for the 1.2 &#x03BC;m and 1.8 &#x03BC;m resist thickness in CMOS photolithography process technology

Statistical parameter evaluation for swing curves for the 1.2 &#x03BC;m and 1.8 &#x03BC;m resist thickness in CMOS photolithography process technology

Gate CD Control Considering Variation of Gate and STI Structure

Platform for collaborative DFM

Contact Info

Product

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Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology

Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology