Gate CD Control Considering Variation of Gate and STI Structure

Kurihara, Masaru; Tanaka, J.; Izawa, Masaru; Kawai, Kenji; Fujiwara, Nobuo

doi:10.1109/tsm.2007.901837

Cited by 10 publications

(3 citation statements)

References 21 publications

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“…the STI thickness beside transistors placed at the edge of array obtains lowered locally and globally. Kurihara et al [12] reported one side effect related to the gate critical dimension (CD) of MOSFET. Using design of experiments, gate CD is modelled as gate

\begin{matrix} right leftthickmathspace.5em \\ normalCD & = - 29.0 + 0.95 \times normalMCD (w, x, y) + 0.10 \\ \times normalPTK (w, x, y) + 0.08 normalSTP (w, x, y) \end{matrix}

masks of critical dimension (MCD), polysilicon thickness (PTK), and shallow trench isolation thickness (steP height) (STP) are the variables of masks CD, polysilicon thickness, and STI step height, respectively.…”

Section: Side Effect Of Sti Cmpmentioning

confidence: 99%

Study on switch‐leakage‐induced dark offset of ambient light sensor

Chae¹

2019

Electron. lett.

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The dark offset which is the reference value of an ambient light sensor is analysed. It varies across the wafer when the temperature is increased because of the leakage current of switch transistors. The difference between before and after wafer revisions shows the clue of leakage current. Modern fabrication processes which change the threshold voltage of switch transistors are surveyed. To explain the discrepancy between test and survey data, some other process issues are discussed.

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\begin{matrix} right leftthickmathspace.5em \\ normalCD & = - 29.0 + 0.95 \times normalMCD (w, x, y) + 0.10 \\ \times normalPTK (w, x, y) + 0.08 normalSTP (w, x, y) \end{matrix}

Section: Side Effect Of Sti Cmpmentioning

confidence: 99%

Study on switch‐leakage‐induced dark offset of ambient light sensor

Chae¹

2019

Electron. lett.

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“…In addition, the interaction among the across-wafer trench depth, the gap-filled oxide deposition, and CMP polish rate distribution requires the optimization of all related processes to minimize the across-wafer step height variation. This is highly critical for improving the gate CD uniformity [4,5] and the gate profile. More details on such correlation are discussed in the next section.…”

Section: Sti Etchmentioning

confidence: 99%

A Study of 65nm Silicon Etch

et al. 2010

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The control of shallow trench isolation (STI) depth uniformity and poly gate profile necessitates the combination of more advanced silicon etch methodologies, in-situ measurements, and various relevant integration schemes. This paper presents a study of the difficulties and corresponding solutions in 65nm silicon etch with respect to process development and mass production. In the development phase, the STI trench profile and the depth uniformity of the STI depth can be well controlled by etch recipe tuning. In the mass production phase, we need to extend additional focus on the impact from different products on the inter-field variation of STI depth. Results show a good correlation of the depth to the pattern density variation. Such relationship has been utilized in feed-forward mode to deliver a robust process control. In addition, we also address the influence of oxide variation in STI fabrication and STI step height difference on the corresponding poly gate profile and the pits defects.

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“…One issue is critical dimension (CD) loss or gain, which is a pattern gap between the mask and etching profiles. 1) For example, the CD variation of gate electrodes, which closely affects the channel length of a transistor and thus device performance, has become increasingly important as integrated circuit device dimensions are scaled down to much less than 100 nm. Thus, a better understanding of plasma-surface interactions during etching continues to be important for the nanoscale control of etched profiles and CDs.…”

Section: Introductionmentioning

confidence: 99%

Effects of Mask Pattern Geometry on Plasma Etching Profiles

Fukumoto

Eriguchi

Ono

2009

Jpn. J. Appl. Phys.

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Two-dimensional etching profile evolution in two different geometries, namely an axisymmetric hole and an infinitely long trench, has been simulated with the cellular algorithm, to clarify the effects of geometrically different structures on etching profile evolution. The simulation assumed SiO 2 etching using CF 4 plasmas, owing to the widely employed fluorocarbon plasmas for the fabrication of contact and via holes. Numerical results indicated that the two mask pattern geometries give some differences in profile evolution, depending on condition parameters such as ion energy, mask pattern size, mask height, and reflection probability on mask surfaces. The profile evolution is slower and more anisotropic in a hole than in a trench; in practice, the profile of a trench tends to have prominent lateral etches such as an undercut and a bowing on sidewalls. Moreover, the reactive ion etching lag is less significant for a hole than for a trench. These differences are ascribed to the geometrical shadowing effects of the structure for neutrals, where the incident flux of neutrals is more significantly reduced in a hole than in a trench. The differences are also attributed to the anisotropy of the velocity distribution of neutrals; in effect, the velocity distribution is more anisotropic in a hole, because more particles interact with mask sidewalls to adsorb or reflect thereon in a hole, so that more anisotropic neutrals are transported onto bottom surfaces after passing mask features.

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Gate CD Control Considering Variation of Gate and STI Structure

Cited by 10 publications

References 21 publications

Study on switch‐leakage‐induced dark offset of ambient light sensor

Study on switch‐leakage‐induced dark offset of ambient light sensor

A Study of 65nm Silicon Etch

Effects of Mask Pattern Geometry on Plasma Etching Profiles

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