Comprehensive and Accurate Parasitic Capacitance Models for Two- and Three-Dimensional CMOS Device Structures

Lacord, J.; Ghibaudo, G.; Bœuf, F.

doi:10.1109/ted.2012.2187454

Cited by 71 publications

(44 citation statements)

References 13 publications

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“…In (3), a represents a fitting parameter, which reflect the fact that the values of the mobility as well as of the coupling capacitance are unknown in the access. This phenomenological model could be associated to theoretical works already presented in the literature, as for example in [11]. As seen on fig.…”

Section: Access Resistance Extractionmentioning

confidence: 82%

New access resistance extraction methodology for 14nm FD-SOI technology

Henry¹,

Cros²,

Rosa³

et al. 2016

2016 International Conference on Microelectronic Test Structures (ICMTS)

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In this work, an improved methodology of access resistance extraction is proposed and applied on dedicated Kelvin test structures from a FD-SOI 14 nm technology. The use of this new approach and these test structures allow to confirm that the parasitic resistance of advanced MOSFET is highly dependent of the gate voltage. This explains the impossibility to decorrelate intrinsic and access components using Y function method for very small gate length transistors. A simple phenomenological model for MOSFETs access resistance is proposed and validated at the drain current level.

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Section: Access Resistance Extractionmentioning

confidence: 82%

New access resistance extraction methodology for 14nm FD-SOI technology

Henry¹,

Cros²,

Rosa³

et al. 2016

2016 International Conference on Microelectronic Test Structures (ICMTS)

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show abstract

“…R ext.k is the small-section resistance through the HDD and extension region from the guideline to the surface between the extension and channel region. Accordingly, R con.k and R ext.k can be expressed as a function of device geometry parameters as (9) and , (10) where ρ c , ρ s , and ρ ext are the resistivities of the silicide, HDD, and extension regions and the f function represents the guideline.…”

Section: A Proposed Model Derivationmentioning

confidence: 99%

“…Recently, Wu et al published a detailed analysis of geometry-dependent gate-capacitive and gateresistive parasitics, conducted with the goal of reducing both the gate fringe capacitance and gate parasitic resistance for n-fin FinFETs [9]; however, the reference model employed in this work did not consider the use of the raised source and drain (RSD) structure and metal contact. Lacord et al have analyzed capacitance models in FinFETs, taking into account the specific technology of RSD structure and metal contact [10]. Dixit et al [7] developed a parasitic source/drain resistance model based on analysis of components of the series resistance in double-gate FinFETs and argued that the contact resistance is the dominant component.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance

An¹,

Choe²,

Kwon³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency (f T ). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.Index Terms-Cutoff frequency, fin field-effect transistors (FinFETs), fringe capacitance, number of gate fingers, number of fins, parasitic resistance, radio frequency (RF).

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“…In sub-14-nm technology node devices, the parasitic capacitances have started to dominate the total MOSFET capacitance [3], [4], which deteriorates both the speed and the power consumption of integrated circuits [5]. This problem may become even more acute in III-V MOSFETs, because they feature a lower density of states [6], which decreases their gate capacitance C g [7].…”

Section: Introductionmentioning

confidence: 99%

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

Hiblot

Rafhay

Bœuf

et al. 2015

IEEE Trans. Electron Devices

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In this paper, the main MOSFET parasitic capacitances of planar devices (i.e., bulk, Fully depleted silicon-on-insulator (FDSOI), and planar double gate) are computed using two successive conformal mapping transforms. First, the structure is mapped to the real axis of the complex plane, and then the second transform, deduced directly from the Schwarz-Christoffel theorem, reduces the capacitance to the trivial parallel electrodes case. This second step involves elliptic integrals, which provide a generic expression for all parasitic capacitances. This method is later compared against other models based on conformal mapping. Finally, the results are validated with finite-element method simulations of the inner and outer fringe capacitances in different architectures, including metallic contacts and raised and faceted junctions.Index Terms-CMOS, compact model, conformal mapping, electrostatic, elliptic integrals, Model for Assessment of CMOS Technologies and Roadmaps (MASTAR), MOSFET, parasitic capacitance, roadmap.

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Comprehensive and Accurate Parasitic Capacitance Models for Two- and Three-Dimensional CMOS Device Structures

Cited by 71 publications

References 13 publications

New access resistance extraction methodology for 14nm FD-SOI technology

New access resistance extraction methodology for 14nm FD-SOI technology

Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

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