Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales

Ebrahimi, Mojtaba; Evans, Adrian; Tahoori, Mehdi B.; Seyyedi, Razi; Costenaro, Enrico; Alexandrescu, Dan

doi:10.7873/date2014.043

Cited by 8 publications

(8 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to investigate the accuracy of the proposed technique, we have used a gate-level Monte-Carlo simulation based fault injection engine called Random Width SET Fault Injection (RWFI) as described in [26]. In RWFI, SETs with random initial widths are injected at the output of random gates at random time during the clock period (i.e.…”

Section: Fault Injection Resultsmentioning

confidence: 99%

“…So, for a realistic and practical comparison between the vulnerability of the circuits to SETs, the circuit designers have to consider SETs with different initial pulse widths. Hence, it is required to repeat the SER estimation methods for the circuits for all initial pulse widths of occurred SETs [26]. This makes the SER estimation approach less inefficient and impractical in comparison to the vulnerability analysis of various combinational circuits.…”

Section: Introductionmentioning

confidence: 99%

“…This weakness becomes more serious when using SER reduction techniques in the circuit design flow. In SER reduction techniques, the designer reduces the soft error vulnerability based on the metric which identifies the most vulnerable circuit gates considering only a specific SET initial width, and ignoring other probable pulse widths [14,26,27,28]. Hence, introducing a new metric for evaluating the combinational circuit vulnerability to soft errors without any assumption on the initial pulse width of SETs will improve the efficiency of soft error rate estimation and reduction processes.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A practical metric for soft error vulnerability analysis of combinational circuits

Raji

Pedram

Ghavami

2015

Microelectronics Reliability

View full text Add to dashboard Cite

Section: Fault Injection Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A practical metric for soft error vulnerability analysis of combinational circuits

Raji

Pedram

Ghavami

2015

Microelectronics Reliability

View full text Add to dashboard Cite

“…The actual failure rate or failure-in-time (FIT) rate depends on the technology [17,26], circuit structure (e.g., logic gate structure, size) [11], operating points (e.g., supply voltage) [7] and ambient conditions (e.g., altitude) [14].…”

Section: Radiation-induced Soft Errormentioning

confidence: 99%

“…Previous work addressed either the hardware reliability modeling challenges [3,11] or proposed new sophisticated power management algorithms [21,25,31]. They focused on a specific hardware model and did not consider the power and reliability impacts of wide varieties of hardware support for power management.…”

Section: Introductionmentioning

confidence: 99%

Evaluating and exploiting impacts of dynamic power management schemes on system reliability

Lai¹,

Chandra²,

Gupta³

2015

2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

View full text Add to dashboard Cite

Hardware reliability has been a major concern for nano-scale computing systems. Different hardware design choices, application workloads and software management schemes can jointly affect the system's resilience. In this paper, we first develop a hardware evaluation platform based on an embedded/mobile development board and standard Linux kernel. We demonstrate the use of our platform to evaluate the system's power and radiation-induced soft error rate in presence of system power management schemes and with different application workloads and various hardware design configurations. We also propose system/cloud-based virtual sensing to capture varying ambient conditions for reliability evaluation. New reliability management policies are proposed and implemented in Linux kernel to exploit the flexibility in different existing power management schemes. We demonstrate that our policies can achieve the system reliability target under varying application workloads and ambient conditions. Experiments show that our policies are efficient and with less than 3% additional power overhead compared to the optimal schemes characterized offline.

show abstract

Reliability Analysis and Mitigation of Near-Threshold Voltage (NTC) Caches

Gebregiorgis

Bishnoi

Tahoori

2020

Dependable Embedded Systems

Self Cite

View full text Add to dashboard Cite

Near-threshold computing (NTC) has significant role in reducing the energy consumption of modern very large-scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This chapter presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near-threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this chapter, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture-level analysis.

show abstract

Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales

Cited by 8 publications

References 0 publications

A practical metric for soft error vulnerability analysis of combinational circuits

A practical metric for soft error vulnerability analysis of combinational circuits

Evaluating and exploiting impacts of dynamic power management schemes on system reliability

Reliability Analysis and Mitigation of Near-Threshold Voltage (NTC) Caches

Contact Info

Product

Resources

About