Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales

Ebrahimi, Mojtaba; Evans, A.; Tahoori, Mehdi B.; Seyyedi, Razi; Costenaro, E.; Alexandrescu, D.

doi:10.7873/date.2014.043

Cited by 22 publications

(13 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As a result the proposed technique for SER reduction is inherently less effective than approaches based on selective replacement with hardened flip-flops [25], [26] where it is common to achieve a 5x SER reduction by replacing fewer than 5% of the flip-flops.…”

Section: Area and Power Constrainted Resultsmentioning

confidence: 99%

Flip-flop SEU reduction through minimization of the temporal vulnerability factor (TVF)

Evans

Costenaro

Bramnik

2015

2015 IEEE 21st International on-Line Testing Symposium (IOLTS)

Self Cite

View full text Add to dashboard Cite

The effects of soft-errors in flip-flops remains a concern in large designs. There exist many radiation hardened flip-flops, however, these are custom cells and not available to all designers. In this paper, we explore a technique for the mitigation of flip-flop soft-errors through an optimization of the temporal vulnerability factor (TVF). By selectively inserting delay on the input or output of flip-flops, the probability of propagation of single event upsets (SEUs) can be minimized. The selection of where to insert the added delay is formulated as a linear programming problem. In this way, the flip-flop soft-error rate (SER) can be minimized subject to overhead constraints. 978-1-4673-7905-2/15/$31.00 c 2015 IEEE

show abstract

Section: Area and Power Constrainted Resultsmentioning

confidence: 99%

Flip-flop SEU reduction through minimization of the temporal vulnerability factor (TVF)

Evans

Costenaro

Bramnik

2015

2015 IEEE 21st International on-Line Testing Symposium (IOLTS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…For SOT-MRAM single-bit error correction is sufficient (lower error rate and random nature of retention failure), according to our results, while for SRAM multi-bit error correction is required to deal with multi-bit upsets in advanced technology nodes. This can be achieved by a combination of single error correction and an appropriate interleaving distance (≥4) [53]. However, such a large interleaving distance might affect the memory aspect ratio and infer additional area and delay penalty for small memory arrays, hence, more sophisticated ECC schemes would be required.…”

Section: Discussionmentioning

confidence: 99%

Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy

Oboril

Bishnoi

Ebrahimi

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

163

View full text Add to dashboard Cite

Magnetic Random Access Memory (MRAM) is a very promising emerging memory technology because of its various advantages such as non-volatility, high density and scalability. In particular, Spin Orbit Torque (SOT) MRAM is gaining interest as it comes along with all the benefits of its predecessor Spin Transfer Torque (STT) MRAM, but is supposed to eliminate some of its shortcomings. Especially the split of read and write paths in SOT-MRAM promises faster access times and lower energy consumption compared to STT-MRAM. In this work, we provide a very detailed analysis of SOT-MRAM at both circuit-and architecture-level. We present a detailed evaluation of performance and energy related parameters and compare the novel SOT-MRAM with several other memory technologies. Our architecture-level analysis shows that a hybridcombination of SRAM for the L1-Data-cache, SOT-MRAM for the L1-Instruction-cache and L2-cache can reduce the energy consumption by 60 % while the performance increases by 1 % compared to an SRAM-only configuration. Moreover, the retention failure probability of SOT-MRAM is 27x smaller than the probability of radiation-induced Soft Errors in SRAM, for a 65 nm technology node. All of these advantages together make SOT-MRAM a viable choice for microprocessor caches.Index Terms-spin orbit torque, non-volatile memory, cache, hybrid, magnetic memory, reliability, failure rate 0278-0070 (c)

show abstract

“…The register file unit, for instance, is always more vulnerable than the WB-multiplexer unit. Ebrahimi, et al also presented an SER analysis of the OpenRISC processor in 45nm technology [26]. Their results show that 75% of the flip-flops within the microprocessor make negligible contributions to the overall system SER, and by protecting the most vulnerable 20% flip-flops, the system SER caused by all the flip-flops can be reduced by 80%.…”

Section: A Soft Error Vulnerability Analysis Of the Openrisc Pipelinementioning

confidence: 98%

A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors

Yang

Zwoliński

Halak

2016

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-The aggressive scaling of semiconductor technology has significantly increased the radiation-induced soft error rate in modern microprocessors. Meanwhile, due to the increasing complexity of modern processor pipelines and the limited errortolerance capabilities that previous radiation hardening techniques can provide, the existing pipeline protection mechanisms cannot achieve complete protection. This paper proposes a complete and cost-effective pipeline protection mechanism using a self-checking architecture. The radiation hardened pipeline is achieved by incorporating SETTOFF-based self-checking cells into the sequential cells of the pipeline. A replay recovery mechanism is also developed at the architectural level to recover the detected errors. The proposed pipeline protection technique is implemented in an OpenRISC microprocessor in 65nm technology. A gate-level transient fault injection and analysis technique is used to evaluate the error-tolerance capability of the proposed hardened pipeline design. The results show that compared to techniques such as TMR, the SETTOFF-based self-checking technique requires over 30% less area and 80% less power overheads. Meanwhile, the error-tolerant and selfchecking capabilities of the register allow the proposed pipeline protection technique to provide a noticeably higher level of reliability for different parts of the pipeline compared to previous pipeline protection techniques.

show abstract

Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales

Cited by 22 publications

References 0 publications

Flip-flop SEU reduction through minimization of the temporal vulnerability factor (TVF)

Flip-flop SEU reduction through minimization of the temporal vulnerability factor (TVF)

Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy

A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors

Contact Info

Product

Resources

About