Component-based system design: analytic real-time interfaces for state-based component implementations

Lampka, Kai; Perathoner, Simon; Thiele, Lothar

doi:10.1007/s10009-012-0257-7

Cited by 13 publications

(17 citation statements)

References 14 publications

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“…With regard to activation pattern bounds, a realtime assume interface states, that constraints are satisfied if a certain arrival curve is not exceeded. This result, together with methods for deriving such interfaces was presented in [24] for state-less, greedy processing and in [15] for TimedAutomata based component models. Contrary to the aforementioned works, the authors of [22] introduced a scheme, which was capable of computing regions of input bounding curves, instead of producing individual (safe) curves for a given component model.…”

Section: Related Workmentioning

confidence: 65%

Multi-mode monitoring for mixed-criticality real-time systems

Neukirchner¹,

Lampka²,

Quinton³

et al. 2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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We present a scheme for monitoring activation patterns of multiple tasks in mixed-criticality real-time systems. Unlike previous approaches, which enforce a single pre-defined activation pattern bound per task, we propose a multi-mode approach, where monitors can dynamically switch between different configurations, depending on the observed activation pattern at other tasks. The required configurations are based on real-time interfaces which we determine through sensitivity analysis. In an evaluation we show, that switching between monitor configurations allows to dynamically reassign timing slack between tasks and thereby achieve better resource utilization and still provide the same timing guarantees.

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Section: Related Workmentioning

confidence: 65%

Multi-mode monitoring for mixed-criticality real-time systems

Neukirchner¹,

Lampka²,

Quinton³

et al. 2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

Self Cite

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“…Nevertheless, as it has been said, the problem in this case is the accuracy of the VHDL model corresponding to the real system, and not a limitation of the procedure here described. To avoid such two-steps approaches that analyse the performance of a system in a second step accomplished after a first one devoted to design the system, interface-based approaches have been previously proposed [24,44] to integrate, in only one step, the system design and analysis. In future works we plan to use the here described analysis strategy in the context of the interface-based approaches.…”

Section: Discussionmentioning

confidence: 99%

System performance evaluation by combining RTC and VHDL simulation: A case study on NICs

Garay

Ortega

Díaz

et al. 2013

Journal of Systems Architecture

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“…This is a crucial as it allows one to replace a complex arrival curve α i by a less complex curve α j , but still guaranteeing the validity of the deduced WCRT. Details on this feature can be found in [11,20].…”

Section: Streams and Their Abstract Representationmentioning

confidence: 99%

“…Such techniques have been introduced in [19,20] for the combination of Timed Automata and RTC. The authors of [3] handle the case of synchronous data-flow component models and RTC and [36] introduces the coupling of parametric Timed Automata and RTC on top of a SMT-based analysis technique for deriving regions of parameters for task activation patterns under which the system is scheduled.…”

Section: Related Workmentioning

confidence: 99%

“…The authors of [3] handle the case of synchronous data-flow component models and RTC and [36] introduces the coupling of parametric Timed Automata and RTC on top of a SMT-based analysis technique for deriving regions of parameters for task activation patterns under which the system is scheduled. Our analysis for real-time tasks in a multicore setting is based on the aforementioned coupling of Timed Automata (TA) [4] and RTC [19,20], where we exploit specific concepts as implemented in the timed model checker Uppaal [7,8]. Yi et al [27] were the first to use TA to represent a system resource (CPU or communication element) as a scheduler model together with a notion of discrete events that trigger the execution of real-time tasks on this scheduler.…”

Section: Related Workmentioning

confidence: 99%

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A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets

et al. 2014

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A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets. Real-time systemshttp://dx.doi.org/10.1007/s11241-014-9211-y Access to the published version may require subscription. N.B. When citing this work, cite the original published paper. Abstract Multicore technology has the potential for drastically increasing productivity of embedded real-time computing. However, joint use of hardware, e.g., caches, memory banks and on-chip buses makes the integration of multiple real-time applications into a single system difficult: resource accesses are exclusive and need to be sequenced. Moreover, resource access schemes of modern off-the-shelf multicore chips are commonly optimized for the average-case, rather than being timing predictable. Real-time analysis for such architectures is complex, as execution times depend on the deployed hardware, as well as on the software executing on other cores. This will ask for significant abstractions in the timing analysis, where the resulting pessimism will lead to over-provisioned system designs and a lowered productivity as the number of applications to be put together into a single architecture needs to be decreased. In response to this, (a) we present a formal approach for bounding the worst-case response time of concurrently executing real-time tasks under resource contention and almost arbitrarily complex resource arbitration policies, with a focus on main memory as shared resource, (b) we present a simulation framework which allows for detailed modeling and empirical evaluation of modern multicore platforms and applications running on top of them, and (c) we present experiments to demonstrate the advantages and disadvantages of the presented methodologies and compare their accuracy. For limiting non-determinism inherent to the occurrence of cache misses, we particularly take advantage from the PRedictable Execution Model (PREM) as discussed in recent works.

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Component-based system design: analytic real-time interfaces for state-based component implementations

Cited by 13 publications

References 14 publications

Multi-mode monitoring for mixed-criticality real-time systems

Multi-mode monitoring for mixed-criticality real-time systems

System performance evaluation by combining RTC and VHDL simulation: A case study on NICs

A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets

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