Chair: Jabulani Nyathi Clock skew and clock distribution are increasingly becoming a major design concern in high performance, high density synchronous systems. Large clock networks are required for efficient clock distribution and they contribute significantly to the power dissipated by the system, while clock skew takes up a considerable percentage of the clock period.Design effort for clock networks is currently estimated to take up 20% of system design time, while power dissipation due to the clock network is reported to be 30% of the total dissipation. It is therefore necessary to investigate the possibilities of other schemes that could results in cost reduction by avoiding complicated architectures while facilitating fast logic.We explore the possibility of managing clock skew and reducing clock loading by applying the hybrid wave-pipelining scheme to a linear feedback shift register. The hybrid wave-pipelining scheme takes advantage of interconnects and data path delays to optimize clock skew and allows the clock to "travel" with its associated data. The system's clock in conjunction with stage delays is used to generate wave-pipelined clocks that have short cycle times and are skew tolerant. The hybrid wave-pipelined clock is designed to mimic the data path elements of the LFSR stage, thus reducing the uncontrolled clock skew, as well as clock loading. Thus, the iv resulting skew is a result of the data path circuitry. A LFSR would provide a good means of measuring clock skew since the common edge of the clock triggers data transfer.Linear feedback shift registers also have numerous common uses including pseudorandom number generator, random pattern generator and analyzer, encryption/decryption and direct sequence spread spectrum for digital signal processing. Their study with different clocking schemes is beneficial as LFSRs are easy to analyze and are found in many applications as mentioned.In this thesis, it is shown that the use of hybrid wave-pipelining provides significant clock skew improvements (six times) compared with a buffered clock design, and also offers improved clock cycle time. There is also potential for a reduction in power dissipation associated with the clock trees, since the scheme reduces the need for complicated clock distribution networks.
