Complex reliability evaluation of voters for fault tolerant designs

Abstract

Hardware Voters are bit voters computing a majority of n input bits. An m-out-of-nhardware bit voter is a circuit with n bit inputs, and I bitoutput y, such that y=l i f at least m-out-of-n inputs bits have the value I . A hardware voter can be constructed as two level AND-OR (equivalently OR-AND and other structures) using CMOS VLSI technology. The goal of the paper is to present Reliability Estimations, Failure Modes and Effects, Criticality Analysis (FMECA) of voting networks at the transistor level, in CMOS VLSI implementation.FMECA is performed using the functional tree of the system, representing the dataflow from the lowest level functional block up to the higher level functional blocks.The main idea of this research is to identifji the best designs of voting circuits in terms of reliability parameters and to identih their critical failures and effects.

Design and analysis of two novel 2-out-of-3 voters

“…Apparently, SV is more reliable than DV. The MTTF ( [9][10]) of two voters is figured out, and shown in (5). It is certain that the reliability of the two voters is high enough for applying to all kinds of domains according to EN50129, and the reliability of SV is approximately DV's 2 times.…”

“…It can be seen that if one input is fault, the voter will also produce a correct output. OUT = AB + BC + CA (1) Some previous researches [5][6][7] used CMOS VLSI technology to construct the majority voter. However, CMOS devices are active, and they will generate hazardous output even if all the inputs are correct.…”