Complementary Resistive Switching Using Metal–Ferroelectric–Metal Tunnel Junctions

Abstract

devices can be scaled down as required by the most aggressive scaling in electronic industry. This is an important advantage compared with electronic memory devices based on electric charge storage. [1][2][3] In fact, the resistive random access memory (RRAM) elements are intensively investigated on the path toward higher memory density and enhanced computing performance, as demanded by present and future information technologies. The socalled passive crossbar array of RS devices constitutes the backbone of RRAMs and reconfigurable logics, and holds promises to become central in the quest for merging logic and memory functions or neuromorphic computing. [4][5][6][7] The crossbar array consists of an array of parallel bottom metallic electrodes and a perpendicular array of top metallic electrodes (so called, word and bit lines) that sandwich at each crossing point, the RS element. By applying suitable voltage at the specified word and bit lines, the state of an RS element is set to LRS (ON) or HRS (OFF). Inherent to this array configuration is that the bottom electrode connects all elements in a row and the top electrode connects all elements in a column. It thus follows that: i) if several elements are in LRS state, when current is used to probe the state of a particular element, charge will leak across all LRS elements (sneak current) thus compromising the reading and ii) the presence of LRS states implies a permanent current leakage and a concomitant Joule dissipation. These intrinsic bottlenecks of crossbar arrays are well recognized and several approaches, such as integration of strongly rectifying elements, [8] were proposed to overcome this drawback. In 2010, Linn et al. [9] proposed a simple solution to solve the sneak problem: connect two RS devices in anti-serial configuration in such a way that if one is in LRS state the other is in the HRS state (so-called complementary resistive switching, CRS). In these circumstances, information is stored not in the state of a single RS element but in the state of distinguishable coupled pair: LRS+HRS and HRS+LRS, representing different logic states ("0" and "1"). Of relevance is that the resulting coupled state is always in a HRS at remanence and thus the sneak and leakage currents are reduced.This novel approach was successfully demonstrated using a variety of materials and RS mechanisms. For instance, it was demonstrated in Pt/SiO 2 /GeSe/Cu [9] and in all-oxides RRAMs. [10][11][12][13][14][15][16] In this approach, data reading is achieved by Complementary resistive switching (CRS) devices are receiving attention because they can potentially solve the current-sneak and current-leakage problems of memory arrays based on resistive switching (RS) elements. It is shown here that a simple anti-serial connection of two ferroelectric tunnel junctions, based on BaTiO 3 , with symmetric top metallic electrodes and a common, floating bottom nanometric film electrode, constitute a CRS memory element. It allows nonvolatile storage of binary states ("1" = "HRS+LRS" and "0" =...

Intrinsic asymmetric ferroelectricity induced giant electroresistance in ZnO/BaTiO3 superlattice

“…Combining density functional theory calculations with non equilibrium Green's function formalism, we investigate the electron transport properties of SrRuO 3 /ZnO/BaTiO 3 /ZnO/SrRuO 3 and SrRuO 3 /ZnO/BaTiO 3 / SrRuO 3 with a giant TER effect of 581% and 112% respectively. Compared to the previous results, [27][28][29][30][31] the TER effect of 581% for the tunnel junction combined ZnO and (111) BaTiO 3 in this article is larger than the highest TER effect of 400% 31 for the previous BaTiO 3 -based tunnel junctions. The junctions combined ZnO and (111) BaTiO 3 may exhibit richer and more novel properties in the future.…”

Polarization and Resistive Switching in Epitaxial 2 nm Hf0.5Zr0.5O2 Tunnel Junctions

“…This results in low tunneling current and high resistance values. Whereas high resistance is desirable for some applications, for instance, in ferroelectric complementary resistive switching devices, 49,50 a sizable current is required to achieve fast and reliable reading operation of memory devices, and a trade-off needs to be found. 3 Different strategies can be followed to reduce the device resistance: first is to use metals with a lower work function to reduce the tunneling barrier height (at the expense of usually higher reactivity of the metal); second is to stimulate Fowler− Nordheim tunneling (at the expense of requiring higher reading voltages); 51 and third is to reduce the barrier thickness.…”

“…This results in low tunneling current and high resistance values. Whereas high resistance is desirable for some applications, for instance, in ferroelectric complementary resistive switching devices, , a sizable current is required to achieve fast and reliable reading operation of memory devices, and a trade-off needs to be found …”

Bi2O2Se-Based Memristor-Aided Logic

“…4 By leveraging their conditional RS properties, logic operations can be executed in multiple device architectures, including one memristor−one resistor (1M1R), 5 one transistor−one RRAM (1T1R), 6 one selector−one RRAM (1S1R), 7 and complementary RS. 8 Based on these structures, noteworthy progress in this area has been achieved, including material implications, 16 logic operations, full adder, flip flop, and shifting register. 9−11 Among most of those strategies, additional selection devices seem to be a requisite for the realization of logical functions in memristor architecture.…”