Compiling for automatically generated instruction set extensions

Abstract

The automatic generation of instruction set extensions (ISEs) to provide application-specific acceleration for embedded processors has been a productive area of research in recent years. The use of automatic algorithms, however, results in instructions that are radically different from those found in conventional ISAs. This has resulted in a gap between the hardware's capabilities and the compiler's ability to exploit them. This paper proposes an innovative high-level compiler pass that uses subgraph isomorphism checking to exploit these complex instructions. Our extended code generator also enables the reuse of ISEs designed for one application in another, which may be a newer version of the same application or a different one from the same domain. Operating in a separate pass permits computationally expensive techniques to be applied that are uniquely suited for mapping complex instructions, but unsuitable for conventional instruction selection. We demonstrate that this targeted use of an expensive algorithm effectively controls overall compilation time. The existing, mature, compiler back-end can then handle the remainder of the compilation. Instructions are automatically produced for 179 benchmarks, resulting in a total of 1965 unique instructions. The high-level pass integrated into the open-source GCC compiler is able to use the instructions produced for each benchmark to obtain an average speed-up of 1.26 for the ENCORE extensible processor.

Pre-architectural performance estimation for ASIP design based on abstract processor models

“…The Matching Process: Searching for CIs has been considered as a subgraph isomorphism problem [21]. The original application of this technique enabled compilation for Each match within this set maps each node of the CI into its corresponding BB node, i.e., a node that performs the same operation.…”

“…In the case of commutative operations, the output of the matching stage will produce several duplicated matches, where the same basic block graph nodes are involved. Moreover, some matches may be found where the subgraph is no longer convex [21]. These matches are not useful for estimation and must be pruned from the match set.…”

Instruction Selection

“…A compromise between flexibility and performance, ASIPs are processors whose instruction sets can be extended with additional instructions, allowing the processor to be-at least partlycustomized for the running program in order to improve code quality. The task of discovering and deciding which instructions to add is commonly referred to as the instruction set extension (ISE) problem, and there exists plenty of research on how to solve this problem (see for example [11,20,31,32,41,47,52,57,78,185,198,259,260,266,353], and see [144] for a recent survey). However, although the ISE problem can be regarded as a generalization of the instruction selection problem-the main difference is that the pattern set is no longer fixed-the prevalent approach is to treat them separately.…”

Free Rider

“…A graph based instruction selection technique has been developed in [13], where the compiler targets automatically generated instruction set extensions, where instruction patterns are not tree shaped, but highly irregular and sometimes larger (up to 12 inputs and 8 outputs) than typical multimedia instructions. The graph pattern matching approach used in this paper is somewhat comparable to that in [13], however, the purpose of our work is to aid the user retargeting an application optimised for a platform other than the current target platform, whereas graph pattern matching is used in [13] to match highly idiosyncratic instructions.…”

“…The graph pattern matching approach used in this paper is somewhat comparable to that in [13], however, the purpose of our work is to aid the user retargeting an application optimised for a platform other than the current target platform, whereas graph pattern matching is used in [13] to match highly idiosyncratic instructions.…”