Compiler techniques for high performance sequentially consistent java programs

Sura, Zehra; Fang, Xing; Wong, Chi-Leung; Midkiff, Samuel P.; Lee, Jaejin; Padua, David

doi:10.1145/1065944.1065947

Cited by 82 publications

(65 citation statements)

References 25 publications

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“…Lee and Padua [15] describe an algorithm based on dominators for inserting memory fences, while Sura et al [27] focus on the more practical aspects, e.g., on how to approximate delay sets by performing cheaper whole-program analyses coupled with an escape analysis. While these works perform much more sophisticated analyses than the ones we implemented, unfortunately none of them comes with a mechanised soundness proof.…”

Section: Related Workmentioning

confidence: 99%

Verifying Fence Elimination Optimisations

Vafeiadis

Nardelli

2011

Static Analysis

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Abstract. We consider simple compiler optimisations for removing redundant memory fences in programs running on top of the x86-TSO relaxed memory model. While the optimisations are performed using standard thread-local control flow analyses, their correctness is subtle and relies on a non-standard global simulation argument. The implementation and the proof of correctness are programmed in Coq as part of CompCertTSO, a fully-fledged certified compiler from a concurrent extension of a C-like language to x86 assembler. In this article, we describe the soundness proof of the optimisations and evaluate their effectiveness.

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Section: Related Workmentioning

confidence: 99%

Verifying Fence Elimination Optimisations

Vafeiadis

Nardelli

2011

Static Analysis

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“…There are compiler techniques to identify race cycles and put fences (e.g., [14,17,19,31]). They are conservative because they only use static information, and typically cause large slowdowns.…”

Section: Other Related Workmentioning

confidence: 99%

“…Other researchers have used the compiler to identify race pairs that could cause SCVs, typically using the Delay Set algorithm, and then insert fences to prevent cycles [12,14,17,19,31]. Since the compiler has limited information, these approaches tend to be very conservative and result in substantial slowdowns.…”

Section: Introductionmentioning

confidence: 99%

Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically

Muzahid

Torrellas

2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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Past work has focused on detecting data races as proxies for Sequential Consistency (SC) violations. However, most data races do not violate SC. In addition, lock-free data structures and synchronization libraries sometimes explicitly employ data races but rely on SC semantics for correctness. Consequently, to uncover SC violations, we need to develop a more precise technique.This paper presents Vulcan, the first hardware scheme to precisely detect SC violations at runtime, in programs running on a relaxed-consistency machine. The scheme leverages cache coherence protocol transactions to dynamically detect cycles in memoryaccess orders across threads. When one such cycle is about to occur, an exception is triggered. For the conditions considered in this paper and with enough hardware, Vulcan suffers neither false positives nor false negatives. In addition, Vulcan induces negligible execution overhead, requires no help from the software, and only takes as input the program executable. Experimental results show that Vulcan detects three new SC violation bugs in the Pthread and Crypt libraries, and in the fmm code from SPLASH-2. Moreover, Vulcan's negligible execution overhead makes it suitable for on-the-fly use.

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“…Shasha and Snir proposed the delay sets algorithm for determining the set of fences to insert [45]. Recent research has further reduced the number of fences required by incorporating analyses that detect which memory locations are possibly accessed by multiple threads [30,46]. Finally, recent work describes a new hardware mechanism called a conditional fence [33], which uses the results of a compiler analysis to dynamically decide whether a given fence in the instruction stream can be safely ignored while still ensuring SC.…”

Section: Guaranteeing End-to-end Sequential Consistencymentioning

confidence: 99%

A case for an SC-preserving compiler

Marino

Singh

Millstein

et al. 2011

Proceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation

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The most intuitive memory consistency model for shared-memory multi-threaded programming is sequential consistency (SC). However, current concurrent programming languages support a relaxed model, as such relaxations are deemed necessary for enabling important optimizations. This paper demonstrates that an SC-preserving compiler, one that ensures that every SC behavior of a compiler-generated binary is an SC behavior of the source program, retains most of the performance benefits of an optimizing compiler. The key observation is that a large class of optimizations crucial for performance are either already SC-preserving or can be modified to preserve SC while retaining much of their effectiveness. An SC-preserving compiler, obtained by restricting the optimization phases in LLVM, a state-of-the-art C/C++ compiler, incurs an average slowdown of 3.8% and a maximum slowdown of 34% on a set of 30 programs from the SPLASH-2, PARSEC, and SPEC CINT2006 benchmark suites.While the performance overhead of preserving SC in the compiler is much less than previously assumed, it might still be unacceptable for certain applications. We believe there are several avenues for improving performance without giving up SC-preservation. In this vein, we observe that the overhead of our SC-preserving compiler arises mainly from its inability to aggressively perform a class of optimizations we identify as eager-load optimizations. This class includes common-subexpression elimination, constant propagation, global value numbering, and common cases of loop-invariant code motion. We propose a notion of interference checks in order to enable eager-load optimizations while preserving SC. Interference checks expose to the compiler a commonly used hardware speculation mechanism that can efficiently detect whether a particular variable has changed its value since last read.

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Compiler techniques for high performance sequentially consistent java programs

Cited by 82 publications

References 25 publications

Verifying Fence Elimination Optimisations

Verifying Fence Elimination Optimisations

Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically

A case for an SC-preserving compiler

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