Compiler Optimization on Instruction Scheduling for a Specialized Real-Time Floating Point Soft-Core Processor

Kirchhoff, Michael; Wagner, Lothar; Fengler, Wolfgang

doi:10.4316/aece.2019.03007

Cited by 1 publication

(2 citation statements)

References 7 publications

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“…e program counter is set to a certain value at fixed clock cycles and thus jumps to the corresponding position in the code, realizing hardware loops. Furthermore, the scheduling is performed at design time by an optimizing assembler [30,31] and not at run time by the soft-core itself. Every time a loop is not unrolled and a hardware loop is realized, the information of where the loop starts (program counter), where it ends, and how often it should be run are provided by the optimizing assembler to the set/reset module during design time.…”

Section: Hardware Loop and Jump Instructionsmentioning

confidence: 99%

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A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

Kirchhoff

Kerling

Streitferdt

et al. 2019

International Journal of Reconfigurable Computing

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Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. When using the full potential of FPGAs, it is possible to dynamically reconfigure parts of them during run time without the need to stop the device. This feature is called dynamic partial reconfiguration (DPR). If the DPR approach is to be applied in a real-time application-specific soft-core processor, an architecture must be created that ensures strict compliance with the real-time constraint at all times. In this paper, a novel method that addresses this problem is introduced, and its realization is described. In the first step, an application-specializable soft-core processor is presented that is capable of solving problems while adhering to hard real-time deadlines. This is achieved by the full design time analyzability of the soft-core processor. Its special architecture and other necessary features are discussed. Furthermore, a method for the optimized generation of partial bitstreams for the DPR as well as its practical implementation in a tool is presented. This tool is able to minimize given bitstreams with the help of a differential frame bitmap. Experiments that realize the DPR within the soft-core framework are presented, with respect to the need for hard real-time capability. Those experiments show a significant resource reduction of about 40% compared to a functionally equivalent non-DPR design.

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Section: Hardware Loop and Jump Instructionsmentioning

confidence: 99%

“…Schematic of one core of the ViSARD multi-soft-core processor (based on[30]). Functionality of the torCombitgen tool.…”

mentioning

confidence: 99%

A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

Kirchhoff

Kerling

Streitferdt

et al. 2019

International Journal of Reconfigurable Computing

View full text Add to dashboard Cite

show abstract

Compiler Optimization on Instruction Scheduling for a Specialized Real-Time Floating Point Soft-Core Processor

Cited by 1 publication

References 7 publications

A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

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