Compiler blockability of numerical algorithms

Carr,; Kennedy, Ewan D.

doi:10.1109/superc.1992.236704

Cited by 61 publications

(58 citation statements)

References 8 publications

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“…Tiling (blocking) is a transformation which combines strip-mining with loop permutation to form small tiles of loop iterations which are executed together to exploit data locality [2,15,36].…”

Section: Tiling Transformationsmentioning

confidence: 99%

Tiling Optimizations for 3D Scientific Computations

Rivera¹,

Tseng²

2000

ACM/IEEE SC 2000 Conference (SC'00)

144

133

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Compiler transformations can significantly improve data locality for many scientific programs. In this paper, we show iterative solvers for partial differential equations (PDEs) in three dimensions require new compiler optimizations not needed for 2D codes, since reuse along the third dimension cannot fit in cachefor larger problem sizes. Tiling is a program transformation compilers can apply to capture this reuse, but successful application of tiling requires selection of non-conflicting tiles and/or padding array dimensions to eliminate conflicts. We present new algorithms and cost models for selecting tiling shapes and array pads. We explain why tiling is rarely needed for 2D PDE solvers, but can be helpful for 3D stencil codes. Experimental results show tiling 3D codes can reduce miss rates and achieve performance improvements of 17-121% for key scientific kernels, including a 27% average improvement for the key computational loop nest in the SPEC/NAS benchmark MGRID.

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Section: Tiling Transformationsmentioning

confidence: 99%

Tiling Optimizations for 3D Scientific Computations

Rivera¹,

Tseng²

2000

ACM/IEEE SC 2000 Conference (SC'00)

144

133

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“…The analysis of data dependencies and reference patterns has been used in a variety of loop transformations to improve locality of reference in the program and reduce accesses to the main memory. Researchers have worked on numerous such re-ordering or transformation techniques to improve the locality of reference in applications like loop interchange [9] [20], loop fusion/fission [20] and loop tiling [6][8] [16].…”

Section: Design Space Exploration Using Static Control Flow Graphsmentioning

confidence: 99%

Instruction Cache Tuning for Embedded Multitasking Applications

Dash

Srikanthan

2009

2009 IEEE/IFIP International Symposium on Rapid System Prototyping

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With the advent of mobile and handheld devices, power consumption in embedded systems has become a key design issue. Recently, it has been shown that cache requirements of the applications vary widely and a significant amount of energy can be saved by tuning the cache parameters according to the needs of the application. To this end, techniques have been proposed to tune the cache for single-task based systems but no work has been done to extend these techniques to multitasking applications. In this research work, we present novel, lightweight and fast techniques for energy-sensitive tuning of the instruction cache hierarchy for multitasking applications. Cache tuning for RTOS-driven multitasking applications is achieved by intelligently separating the user tasks and RTOS components and profiling them in isolation to identify the nature of loops in them. We then apply the proposed techniques to tune a predictor based filter cache hierarchy for instructions for both single-task based applications and RTOS-driven multitasking applications. The proposed techniques are able to identify optimal or near-optimal filter and L1 cache sizes for all the applications tested and are up to an order of magnitude faster than exhaustive cache hierarchy simulation techniques. The proposed techniques are also highly scalable and can be relied upon to predict the instruction cache hit rate for any range of instruction cache sizes after a one-time simulation and profiling.

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“…For cache optimizations, a variety of sophisticated static models have been developed for kernels like matrix multiply to help understand cache behavior, to predict optimal tile sizes, and to transform loops to improve temporal locality [29,36,53,95,18,59,16]. Some of these models are expensive to evaluate due to the complexity of accurately modeling interactions between the processor and various levels of the memory hierarchy [62].…”

Section: Factors Influencing Matrix Multiply Performancementioning

confidence: 99%

Statistical Models for Empirical Search-Based Performance Tuning

Vuduc

Demmel

Bilmes

2004

The International Journal of High Performance Computing Applica

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Achieving peak performance from the computational kernels that dominate application performance often requires extensive machine-dependent tuning by hand. Automatic tuning systems have emerged in response, and they typically operate by (1) generating a large number of possible, reasonable implementations of a kernel, and (2) selecting the fastest implementation by a combination of heuristic modeling, heuristic pruning, and empirical search (i.e., actually running the code). This paper presents quantitative data that motivates the development of such a search-based system, using dense matrix multiply as a case study. The statistical distributions of performance within spaces of reasonable implementations, when observed on a variety of hardware platforms, lead us to pose and address two general problems which arise during the search process. First, we develop a heuristic for stopping an exhaustive compile-time search early if a near-optimal implementation is found. Second, we show how to construct run-time decision rules, based on run-time inputs, for selecting from among a subset of the best implementations when the space of inputs can be described by continuously varying features. We address both problems by using statistical modeling techniques that exploit the large amount of performance data collected during the search. We demonstrate these methods on actual performance data collected by the PHiPAC tuning system for dense matrix multiply.We close with a survey of recent projects that use or otherwise advocate an empirical search-based approach to code generation and algorithm selection, whether at the level of computational kernels, compiler and run-time systems, or problem-solving environments. Collectively, these efforts suggest a number of possible software architectures for constructing platform-adapted libraries and applications.

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Compiler blockability of numerical algorithms

Cited by 61 publications

References 8 publications

Tiling Optimizations for 3D Scientific Computations

Tiling Optimizations for 3D Scientific Computations

Instruction Cache Tuning for Embedded Multitasking Applications

Statistical Models for Empirical Search-Based Performance Tuning

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